Lines Matching refs:dev_priv
206 parse_lfp_panel_data(struct drm_i915_private *dev_priv,
221 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither;
235 dev_priv->vbt.lvds_vbt = 1;
247 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
269 dev_priv->lvds_downclock_avail = 1;
270 dev_priv->lvds_downclock = downclock * 10;
283 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
285 dev_priv->vbt.bios_lvds_val);
292 parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
325 dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
346 parse_general_features(struct drm_i915_private *dev_priv,
349 struct drm_device *dev = dev_priv->dev;
354 dev_priv->vbt.int_tv_support = general->int_tv_support;
355 dev_priv->vbt.int_crt_support = general->int_crt_support;
356 dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
357 dev_priv->vbt.lvds_ssc_freq =
359 dev_priv->vbt.display_clock_mode = general->display_clock_mode;
360 dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
364 dev_priv->vbt.int_tv_support,
365 dev_priv->vbt.int_crt_support,
366 dev_priv->vbt.lvds_use_ssc,
367 dev_priv->vbt.lvds_ssc_freq,
368 dev_priv->vbt.display_clock_mode,
369 dev_priv->vbt.fdi_rx_polarity_inverted);
374 parse_general_definitions(struct drm_i915_private *dev_priv,
386 dev_priv->vbt.crt_ddc_pin = bus_pin;
395 parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
450 p_mapping = &(dev_priv->sdvo_mappings[p_child->dvo_port - 1]);
485 parse_driver_features(struct drm_i915_private *dev_priv,
488 struct drm_device *dev = dev_priv->dev;
497 dev_priv->vbt.edp_support = 1;
500 dev_priv->render_reclock_avail = true;
504 parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
512 if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->vbt.edp_support)
519 dev_priv->vbt.edp_bpp = 18;
522 dev_priv->vbt.edp_bpp = 24;
525 dev_priv->vbt.edp_bpp = 30;
533 dev_priv->vbt.edp_pps = *edp_pps;
535 dev_priv->vbt.edp_rate = edp_link_params->rate ? DP_LINK_BW_2_7 :
539 dev_priv->vbt.edp_lanes = 1;
542 dev_priv->vbt.edp_lanes = 2;
546 dev_priv->vbt.edp_lanes = 4;
551 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
554 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
557 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
560 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
565 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400;
568 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600;
571 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800;
574 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200;
580 parse_device_mapping(struct drm_i915_private *dev_priv,
622 dev_priv->vbt.child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL);
623 if (!dev_priv->vbt.child_dev) {
628 dev_priv->vbt.child_dev_num = count;
636 child_dev_ptr = dev_priv->vbt.child_dev + count;
645 init_vbt_defaults(struct drm_i915_private *dev_priv)
647 struct drm_device *dev = dev_priv->dev;
649 dev_priv->vbt.crt_ddc_pin = GMBUS_PORT_VGADDC;
652 dev_priv->vbt.lvds_dither = 1;
653 dev_priv->vbt.lvds_vbt = 0;
656 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
659 dev_priv->vbt.int_tv_support = 1;
660 dev_priv->vbt.int_crt_support = 1;
663 dev_priv->vbt.lvds_use_ssc = 1;
664 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
665 DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->vbt.lvds_ssc_freq);
680 struct drm_i915_private *dev_priv = dev->dev_private;
688 init_vbt_defaults(dev_priv);
691 if (dev_priv->opregion.vbt) {
692 struct vbt_header *vbt = dev_priv->opregion.vbt;
698 dev_priv->opregion.vbt = NULL;
728 parse_general_features(dev_priv, bdb);
729 parse_general_definitions(dev_priv, bdb);
730 parse_lfp_panel_data(dev_priv, bdb);
731 parse_sdvo_panel_data(dev_priv, bdb);
732 parse_sdvo_device_mapping(dev_priv, bdb);
733 parse_device_mapping(dev_priv, bdb);
734 parse_driver_features(dev_priv, bdb);
735 parse_edp(dev_priv, bdb);
748 struct drm_i915_private *dev_priv = dev->dev_private;