Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/i915

Lines Matching refs:dev
37 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
39 	struct drm_i915_private *dev_priv = dev->dev_private;
45 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
47 	struct drm_i915_private *dev_priv = dev->dev_private;
54 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
56 	struct drm_i915_private *dev_priv = dev->dev_private;
63 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
65 	struct drm_i915_private *dev_priv = dev->dev_private;
71 static void i915_save_vga(struct drm_device *dev)
73 	struct drm_i915_private *dev_priv = dev->dev_private;
81 	dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
99 	i915_write_indexed(dev, cr_index, cr_data, 0x11,
100 			   i915_read_indexed(dev, cr_index, cr_data, 0x11) &
104 			i915_read_indexed(dev, cr_index, cr_data, i);
112 		dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
120 			i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
123 		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
125 		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
127 		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
132 			i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
135 static void i915_restore_vga(struct drm_device *dev)
137 	struct drm_i915_private *dev_priv = dev->dev_private;
142 	I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
164 		i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
169 	i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
171 		i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
175 		i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
178 	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
180 	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
182 	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
188 		i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
197 static void i915_save_display(struct drm_device *dev)
199 	struct drm_i915_private *dev_priv = dev->dev_private;
203 	if (INTEL_INFO(dev)->gen <= 4)
208 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
209 		i915_save_display_reg(dev);
214 	if (HAS_PCH_SPLIT(dev)) {
220 		if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
227 		if (INTEL_INFO(dev)->gen >= 4)
229 		if (IS_MOBILE(dev) && !IS_I830(dev))
235 	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
238 	if (HAS_PCH_SPLIT(dev)) {
249 	if (I915_HAS_FBC(dev)) {
250 		if (HAS_PCH_SPLIT(dev)) {
252 		} else if (IS_GM45(dev)) {
262 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
263 		i915_save_vga(dev);
266 static void i915_restore_display(struct drm_device *dev)
268 	struct drm_i915_private *dev_priv = dev->dev_private;
273 	if (INTEL_INFO(dev)->gen <= 4)
276 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
277 		i915_restore_display_reg(dev);
282 	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
285 	if (drm_core_check_feature(dev, DRIVER_MODESET))
288 	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
290 	else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
293 	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
296 	if (HAS_PCH_SPLIT(dev)) {
323 	intel_disable_fbc(dev);
324 	if (I915_HAS_FBC(dev)) {
325 		if (HAS_PCH_SPLIT(dev)) {
327 		} else if (IS_GM45(dev)) {
337 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
338 		i915_restore_vga(dev);
340 		i915_redisable_vga(dev);
343 int i915_save_state(struct drm_device *dev)
345 	struct drm_i915_private *dev_priv = dev->dev_private;
348 	pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
350 	mutex_lock(&dev->struct_mutex);
352 	i915_save_display(dev);
354 	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
356 		if (HAS_PCH_SPLIT(dev)) {
372 	intel_disable_gt_powersave(dev);
388 	mutex_unlock(&dev->struct_mutex);
393 int i915_restore_state(struct drm_device *dev)
395 	struct drm_i915_private *dev_priv = dev->dev_private;
398 	pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
400 	mutex_lock(&dev->struct_mutex);
402 	i915_gem_restore_fences(dev);
403 	i915_restore_display(dev);
405 	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
407 		if (HAS_PCH_SPLIT(dev)) {
434 	mutex_unlock(&dev->struct_mutex);
436 	intel_i2c_reset(dev);