Lines Matching refs:pm_iir
668 u32 pm_iir, pm_imr;
672 pm_iir = dev_priv->rps.pm_iir;
673 dev_priv->rps.pm_iir = 0;
678 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
683 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
801 u32 pm_iir)
809 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
816 dev_priv->rps.pm_iir |= pm_iir;
817 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
889 u32 pm_iir)
894 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
895 if (dev_priv->rps.pm_iir) {
896 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
904 if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
905 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
908 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
909 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
920 u32 iir, gt_iir, pm_iir;
931 pm_iir = I915_READ(GEN6_PMIIR);
933 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
984 if (pm_iir & GEN6_PM_RPS_EVENTS)
985 gen6_queue_rps_work(dev_priv, pm_iir);
988 I915_WRITE(GEN6_PMIIR, pm_iir);
1140 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
1217 pm_iir = I915_READ(GEN6_PMIIR);
1218 if (pm_iir) {
1220 hsw_pm_irq_handler(dev_priv, pm_iir);
1221 else if (pm_iir & GEN6_PM_RPS_EVENTS)
1222 gen6_queue_rps_work(dev_priv, pm_iir);
1223 I915_WRITE(GEN6_PMIIR, pm_iir);
1260 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
1280 pm_iir = I915_READ(GEN6_PMIIR);
1282 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
1339 if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
1340 gen6_queue_rps_work(dev_priv, pm_iir);
1344 I915_WRITE(GEN6_PMIIR, pm_iir);