Lines Matching refs:mask
85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
89 if ((dev_priv->irq_mask & mask) != 0) {
90 dev_priv->irq_mask &= ~mask;
97 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
101 if ((dev_priv->irq_mask & mask) != mask) {
102 dev_priv->irq_mask |= mask;
221 * the other pipes, due to the fact that there's just one interrupt mask/enable
264 * one interrupt mask/enable bit for all the transcoders.
318 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
323 if ((pipestat & mask) == mask)
327 pipestat |= mask | (mask >> 16);
333 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
338 if ((pipestat & mask) == 0)
341 pipestat &= ~mask;
812 * The mask bit in IMR is cleared by dev_priv->rps.work.
897 /* never want to mask useful interrupts. (also posting read) */
1169 /* On Haswell, also mask ERR_INT because we don't want to risk
2059 * mask them.
2629 u32 mask = ~I915_READ(SDEIMR);
2633 mask &= ~SDE_HOTPLUG_MASK;
2636 mask |= hpd_ibx[intel_encoder->hpd_pin];
2638 mask &= ~SDE_HOTPLUG_MASK_CPT;
2641 mask |= hpd_cpt[intel_encoder->hpd_pin];
2644 I915_WRITE(SDEIMR, ~mask);
2663 u32 mask;
2669 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2672 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2678 I915_WRITE(SDEIMR, ~mask);
3324 * Enable some error detection, note the instruction error mask