Lines Matching defs:bit
146 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
150 ironlake_enable_display_irq(dev_priv, bit);
152 ironlake_disable_display_irq(dev_priv, bit);
179 uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
183 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
185 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
222 * bit for all the pipes.
264 * one interrupt mask/enable bit for all the transcoders.
812 * The mask bit in IMR is cleared by dev_priv->rps.work.
1388 * the reset in-progress bit is only ever set by code outside of this
2378 * If so we can simply poke the RB_WAIT bit
2998 /* Can't rely on pipestat interrupt bit in iir as it might
3000 * It doesn't set the bit in iir again, but it still produces
3171 /* Can't rely on pipestat interrupt bit in iir as it might
3173 * It doesn't set the bit in iir again, but it still produces
3232 * transitions from zero to nonzero. If another bit got
3325 * bit is reserved, so we leave it masked.
3404 /* Can't rely on pipestat interrupt bit in iir as it might
3406 * It doesn't set the bit in iir again, but it still produces
3470 * transitions from zero to nonzero. If another bit got
3573 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */