Cross Reference: /solaris-x11-s11/open-src/app/mkcookie/sun-src/mkcookie.c

Lines Matching refs:dev
55 static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
82 static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev,
100 static gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev,
135 i915_ppgtt_page_alloc(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt,
146 	if (ddi_dma_alloc_handle(dev->devinfo, &ppgt_dma_attr,
203 	struct drm_i915_private *dev_priv = ppgtt->dev->dev_private;
227 static int gen6_ppgtt_enable(struct drm_device *dev)
229 	drm_i915_private_t *dev_priv = dev->dev_private;
243 	if (INTEL_INFO(dev)->gen == 6) {
257 	} else if (INTEL_INFO(dev)->gen >= 7) {
264 		if (IS_HASWELL(dev)) {
275 		if (INTEL_INFO(dev)->gen >= 7)
295 	scratch_pte = ppgtt->pte_encode(ppgtt->dev,
327 		pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, pages[j] << PAGE_SHIFT,
350 	struct drm_device *dev = ppgtt->dev;
351 	struct drm_i915_private *dev_priv = dev->dev_private;
360 	if (IS_HASWELL(dev)) {
362 	} else if (IS_VALLEYVIEW(dev)) {
372 	ret = i915_ppgtt_page_alloc(dev, ppgtt, ppgtt->num_pd_entries);
385 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
387 	struct drm_i915_private *dev_priv = dev->dev_private;
395 	ppgtt->dev = dev;
398 	if (INTEL_INFO(dev)->gen < 8)
413 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
415 	struct drm_i915_private *dev_priv = dev->dev_private;
445 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
447 	struct drm_i915_private *dev_priv = dev->dev_private;
461 	i915_gem_chipset_flush(dev);
470 	if (!dma_map_sg(&obj->base.dev->pdev->dev,
488 	struct drm_device *dev = obj->base.dev;
489 	struct drm_i915_private *dev_priv = dev->dev_private;
503 			    dev_priv->gtt.pte_encode(dev, page_addr, level));
519 			dev_priv->gtt.pte_encode(dev, page_addr, level));
530 static void gen6_ggtt_clear_range(struct drm_device *dev,
534 	struct drm_i915_private *dev_priv = dev->dev_private;
551 		scratch_pte = dev_priv->gtt.pte_encode(dev, scratch_page_addr, I915_CACHE_LLC);
560 	struct drm_device *dev = obj->base.dev;
565 	(void) drm_agp_bind_pages(dev,
572 static void i915_ggtt_clear_range(struct drm_device *dev,
576 	struct drm_i915_private *dev_priv = dev->dev_private;
579 		(void) drm_agp_unbind_pages(dev, obj->base.pfnarray,
591 	struct drm_device *dev = obj->base.dev;
592 	struct drm_i915_private *dev_priv = dev->dev_private;
600 	struct drm_device *dev = obj->base.dev;
601 	struct drm_i915_private *dev_priv = dev->dev_private;
603 	dev_priv->gtt.gtt_clear_range(dev, obj, type);
629 void i915_gem_setup_global_gtt(struct drm_device *dev,
643 	drm_i915_private_t *dev_priv = dev->dev_private;
648 	if (!HAS_LLC(dev))
670 intel_enable_ppgtt(struct drm_device *dev)
676 	if (INTEL_INFO(dev)->gen == 6)
682 void i915_gem_init_global_gtt(struct drm_device *dev)
684 	struct drm_i915_private *dev_priv = dev->dev_private;
690 	if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
692 		if (INTEL_INFO(dev)->gen <= 7) {
698 	i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
700 	setup_scratch_page(dev);
702 	if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
704 		ret = i915_gem_init_aliasing_ppgtt(dev);
714 int setup_scratch_page(struct drm_device *dev)
716 	struct drm_i915_private *dev_priv = dev->dev_private;
724 	if (IS_G33(dev))
727 		gen = INTEL_INFO(dev)->gen * 10;
729 	if (drm_gem_object_init(dev, dev_priv->gtt.scratch_page, DRM_PAGE_SIZE, gen) != 0) {
738 void teardown_scratch_page(struct drm_device *dev)
740 	struct drm_i915_private *dev_priv = dev->dev_private;
769 static void i915_gen6_gtt_ioremap(struct drm_local_map *map, struct drm_device *dev)
774 	ret = ddi_regs_map_setup(dev->devinfo, GEN6_GTTMMADR,
785 static int gen6_gmch_probe(struct drm_device *dev,
789 	struct drm_i915_private *dev_priv = dev->dev_private;
793 	dev_priv->gtt.mappable_end = pci_resource_len(dev->pdev, 1);
805 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
813 	dev_priv->gtt.gtt_mapping.offset = dev->agp_aperbase;
819 	i915_gen6_gtt_ioremap(&dev_priv->gtt.gtt_mapping, dev);
833 static void gen6_gmch_remove(struct drm_device *dev)
835 	struct drm_i915_private *dev_priv = dev->dev_private;
836 	drm_core_ioremapfree(&dev_priv->gtt.gtt_mapping, dev);
840 intel_gtt_stolen_size(struct drm_device *dev)
847 	drm_i915_private_t *dev_priv = dev->dev_private;
849 	if ( INTEL_INFO(dev)->gen == 1)
855 	if (dev->pdev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
856 	    dev->pdev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
936 intel_gtt_mappable_entries(struct drm_device *dev)
939 	drm_i915_private_t *dev_priv = dev->dev_private;
941 	if (INTEL_INFO(dev)->gen == 1) {
944 		pci_read_config_dword(dev->pdev,
952 	} else if (INTEL_INFO(dev)->gen == 2) {
964 		aperture_size = pci_resource_len(dev->pdev,
965 			(IS_G33(dev) || IS_I945GM(dev)) ? 2 : 1);  /* OSOL_i915 */
973 i965_adjust_pgetbl_size(struct drm_device *dev, unsigned int size_flag)
976 	drm_i915_private_t *dev_priv = dev->dev_private;
991 i965_gtt_total_entries(struct drm_device *dev)
996 	drm_i915_private_t *dev_priv = dev->dev_private;
1001 	if (INTEL_INFO(dev)->gen == 5) {
1005 			i965_adjust_pgetbl_size(dev, I965_PGETBL_SIZE_1MB);
1008 			i965_adjust_pgetbl_size(dev, I965_PGETBL_SIZE_1_5MB);
1012 			i965_adjust_pgetbl_size(dev, I965_PGETBL_SIZE_2MB);
1048 intel_gtt_total_entries(struct drm_device *dev)
1050 	drm_i915_private_t *dev_priv = dev->dev_private;
1052 	if (IS_G33(dev) || INTEL_INFO(dev)->gen == 4 || INTEL_INFO(dev)->gen == 5)
1053 		return i965_gtt_total_entries(dev);
1062 static int i915_gmch_probe(struct drm_device *dev,
1066 	struct drm_i915_private *dev_priv = dev->dev_private;
1068 	dev_priv->gtt.mappable_end = intel_gtt_mappable_entries(dev) << PAGE_SHIFT;
1069 	*gtt_total = intel_gtt_total_entries(dev) << PAGE_SHIFT;
1070 	*stolen = intel_gtt_stolen_size(dev);
1078 static void i915_gmch_remove(struct drm_device *dev)
1083 int i915_gem_gtt_init(struct drm_device *dev)
1085 	struct drm_i915_private *dev_priv = dev->dev_private;
1089 	gtt->mappable_base = dev->agp_aperbase;	
1091 	if (INTEL_INFO(dev)->gen <= 5) {
1097 		if (IS_HASWELL(dev)) {
1099 		} else if (IS_VALLEYVIEW(dev)) {
1106 	ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
1123 intel_rw_gtt(struct drm_device *dev,
1129 	struct drm_i915_private *dev_priv = dev->dev_private;
1136 	if (INTEL_INFO(dev)->gen <= 5) {
1137 		(void) drm_agp_rw_gtt(dev, size/PAGE_SIZE, gtt_offset,
1158 i915_clean_gtt(struct drm_device *dev, size_t offset)
1160 	struct drm_i915_private *dev_priv = dev->dev_private;
1167 	if (INTEL_INFO(dev)->gen <= 5) {
1168 		(void) drm_agp_unbind_pages(dev, NULL, num_entries,
1174 			scratch_pte = gen6_pte_encode(dev, scratch_page_addr, I915_CACHE_LLC);