Lines Matching refs:dev
127 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
129 #define for_each_encoder_on_crtc(dev, __crtc, _intel_encoder) \
130 list_for_each_entry((_intel_encoder), struct intel_encoder, &(dev)->mode_config.encoder_list, base.head) \
344 bool (*fbc_enabled)(struct drm_device *dev);
346 void (*disable_fbc)(struct drm_device *dev);
347 int (*get_display_clock_speed)(struct drm_device *dev);
348 int (*get_fifo_size)(struct drm_device *dev, int plane);
367 void (*update_wm)(struct drm_device *dev);
368 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
371 void (*modeset_global_resources)(struct drm_device *dev);
385 void (*init_clock_gating)(struct drm_device *dev);
386 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
391 void (*hpd_irq_setup)(struct drm_device *dev);
476 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
478 void (*gtt_remove)(struct drm_device *dev);
479 void (*gtt_clear_range)(struct drm_device *dev,
484 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
493 struct drm_device *dev;
509 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
512 int (*enable)(struct drm_device *dev);
753 * dev->struct mutext. */
927 /* Protected by the above dev->gpu_error.lock. */
1011 struct drm_device *dev;
1020 * with dev->struct_mutex. */
1262 * Protected by dev->struct_mutex.
1429 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1431 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1432 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1433 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1434 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1435 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1436 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1437 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1438 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1439 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1440 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1441 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1442 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1443 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1444 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1445 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1446 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1447 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1448 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1449 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1450 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1451 (dev)->pci_device == 0x0152 || \
1452 (dev)->pci_device == 0x015a)
1453 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1454 (dev)->pci_device == 0x0106 || \
1455 (dev)->pci_device == 0x010A)
1456 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1457 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1458 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1459 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1460 ((dev)->pci_device & 0xFF00) == 0x0A00)
1468 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1469 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1470 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1471 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1472 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1473 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1475 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1476 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1477 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1478 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1479 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1481 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1482 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1484 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1485 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1488 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1493 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1494 IS_I915GM(dev)))
1495 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1496 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1497 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1498 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1499 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1500 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1502 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1504 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1505 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1506 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1508 #define HAS_IPS(dev) (IS_ULT(dev))
1510 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1512 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1513 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1514 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1523 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1524 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1525 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1526 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1527 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1528 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1530 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1532 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1576 extern int i915_suspend(struct drm_device *dev);
1577 extern int i915_resume(struct drm_device *dev);
1578 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1579 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1580 extern void i915_driver_entervt(struct drm_device *dev);
1581 extern void i915_driver_leavevt(struct drm_device *dev);
1582 extern void i915_driver_agp_support_detect(struct drm_device *dev, unsigned long flags);
1585 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1586 extern void i915_kernel_lost_context(struct drm_device * dev);
1589 extern int i915_driver_firstopen(struct drm_device *dev);
1590 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1591 extern void i915_driver_lastclose(struct drm_device * dev);
1592 extern void i915_driver_preclose(struct drm_device *dev,
1594 extern void i915_driver_postclose(struct drm_device *dev,
1596 extern int i915_driver_device_is_agp(struct drm_device * dev);
1601 extern int i915_emit_box(struct drm_device *dev,
1604 extern int intel_gpu_reset(struct drm_device *dev);
1605 extern int i915_reset(struct drm_device *dev);
1609 extern void i915_emit_mi_flush(drm_device_t *dev, uint32_t flush);
1616 void i915_handle_error(struct drm_device *dev, bool wedged);
1618 extern void intel_irq_init(struct drm_device *dev);
1619 extern void intel_pm_init(struct drm_device *dev);
1620 extern void intel_hpd_init(struct drm_device *dev);
1621 extern void intel_gt_init(struct drm_device *dev);
1622 extern void intel_gt_sanitize(struct drm_device *dev);
1633 extern void i915_destroy_error_state(struct drm_device *dev);
1662 void i915_gem_load(struct drm_device *dev);
1666 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1676 void i915_gem_lastclose(struct drm_device *dev);
1689 int i915_mutex_lock_interruptible(struct drm_device *dev);
1696 struct drm_device *dev,
1698 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1700 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1711 int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1712 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1720 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1731 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1736 void i915_gem_retire_requests(struct drm_device *dev);
1751 void i915_gem_reset(struct drm_device *dev);
1757 int i915_gem_init(struct drm_device *dev);
1758 int i915_gem_init_hw(struct drm_device *dev);
1759 void i915_gem_l3_remap(struct drm_device *dev);
1760 void i915_gem_init_swizzling(struct drm_device *dev);
1761 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1762 int i915_gpu_idle(struct drm_device *dev);
1763 int i915_gem_idle(struct drm_device *dev, uint32_t type);
1781 int i915_gem_attach_phys_object(struct drm_device *dev,
1785 void i915_gem_detach_phys_object(struct drm_device *dev,
1787 void i915_gem_free_all_phys_object(struct drm_device *dev);
1788 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1791 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1793 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1798 void i915_gem_restore_fences(struct drm_device *dev);
1801 void i915_gem_context_init(struct drm_device *dev);
1802 void i915_gem_context_fini(struct drm_device *dev);
1803 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1818 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1825 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1831 void i915_gem_init_global_gtt(struct drm_device *dev);
1832 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1834 int setup_scratch_page(struct drm_device *dev);
1835 void teardown_scratch_page(struct drm_device *dev);
1836 int i915_gem_gtt_init(struct drm_device *dev);
1837 void intel_rw_gtt(struct drm_device *dev, size_t size,
1839 void i915_clean_gtt(struct drm_device *dev, size_t offset);
1840 void i915_gem_chipset_flush(struct drm_device *dev);
1843 int i915_gem_evict_something(struct drm_device *dev, int min_size,
1848 int i915_gem_evict_everything(struct drm_device *dev);
1851 int i915_gem_init_stolen(struct drm_device *dev);
1852 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1853 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1854 void i915_gem_cleanup_stolen(struct drm_device *dev);
1856 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1858 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1867 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1873 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1879 uint32_t hw_offset, struct drm_device *dev);
1880 void register_dump(struct drm_device *dev);
1881 void gtt_dump(struct drm_device *dev);
1882 void ring_dump(struct drm_device *dev, struct intel_ring_buffer *ring);
1885 int i915_verify_lists(struct drm_device *dev);
1887 #define i915_verify_lists(dev) 0
1895 extern int i915_save_state(struct drm_device *dev);
1896 extern int i915_restore_state(struct drm_device *dev);
1899 void i915_save_display_reg(struct drm_device *dev);
1900 void i915_restore_display_reg(struct drm_device *dev);
1903 extern int intel_setup_gmbus(struct drm_device *dev);
1904 extern void intel_teardown_gmbus(struct drm_device *dev);
1918 extern void intel_i2c_reset(struct drm_device *dev);
1922 extern void intel_modeset_init_hw(struct drm_device *dev);
1923 extern void intel_modeset_suspend_hw(struct drm_device *dev);
1924 extern void intel_modeset_init(struct drm_device *dev);
1925 extern void intel_modeset_gem_init(struct drm_device *dev);
1926 extern void intel_modeset_cleanup(struct drm_device *dev);
1927 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1928 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1930 extern void i915_redisable_vga(struct drm_device *dev);
1931 extern bool intel_fbc_enabled(struct drm_device *dev);
1932 extern void intel_disable_fbc(struct drm_device *dev);
1933 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1934 extern void intel_init_pch_refclk(struct drm_device *dev);
1935 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1936 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
1939 extern void intel_detect_pch (struct drm_device *dev);
1941 extern int intel_enable_rc6(const struct drm_device *dev);
1944 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1949 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1952 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1954 struct drm_device *dev,
2030 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2032 if (HAS_PCH_SPLIT(dev))
2034 else if (IS_VALLEYVIEW(dev))