Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/i915

Lines Matching refs:dev_priv
51 	intel_ring_begin(LP_RING(dev_priv), (n))
54 	intel_ring_emit(LP_RING(dev_priv), x)
57 	intel_ring_advance(LP_RING(dev_priv))
71 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
73 	if (I915_NEED_GFX_HWS(dev_priv->dev)) {
74 		u32 *regs = (u32 *)dev_priv->dri1.gfx_hws_cpu_addr.handle;
77 		return intel_read_status_page(LP_RING(dev_priv), reg);
80 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
81 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
86 	drm_i915_private_t *dev_priv = dev->dev_private;
93 				READ_BREADCRUMB(dev_priv);
99 	drm_i915_private_t *dev_priv = dev->dev_private;
102 	addr = dev_priv->status_page_dmah->paddr;
104 		addr |= (dev_priv->status_page_dmah->paddr >> 28) & 0xf0;
114 	drm_i915_private_t *dev_priv = dev->dev_private;
115 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
117 	if (dev_priv->status_page_dmah) {
118 		drm_pci_free(dev_priv->status_page_dmah);
119 		dev_priv->status_page_dmah = NULL;
124 		drm_core_ioremapfree(&dev_priv->dri1.gfx_hws_cpu_addr, dev);
133 	drm_i915_private_t *dev_priv = dev->dev_private;
135 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
160 	drm_i915_private_t *dev_priv = dev->dev_private;
172 		intel_cleanup_ring_buffer(&dev_priv->ring[i]);
184 	drm_i915_private_t *dev_priv = dev->dev_private;
197 		if (LP_RING(dev_priv)->obj != NULL) {
213 	dev_priv->dri1.cpp = init->cpp;
214 	dev_priv->dri1.back_offset = init->back_offset;
215 	dev_priv->dri1.front_offset = init->front_offset;
216 	dev_priv->dri1.current_page = 0;
222 	dev_priv->dri1.allow_batchbuffer = 1;
229 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
230 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
355 	drm_i915_private_t *dev_priv = dev->dev_private;
358 	if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
387 	struct drm_i915_private *dev_priv = dev->dev_private;
429 	drm_i915_private_t *dev_priv = dev->dev_private;
432 	dev_priv->dri1.counter++;
433 	if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
434 		dev_priv->dri1.counter = 0;
436 		master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
441 		OUT_RING(dev_priv->dri1.counter);
485 	struct drm_i915_private *dev_priv = dev->dev_private;
545 	drm_i915_private_t *dev_priv = dev->dev_private;
555 			 dev_priv->dri1.current_page,
569 	if (dev_priv->dri1.current_page == 0) {
570 		OUT_RING(dev_priv->dri1.back_offset);
571 		dev_priv->dri1.current_page = 1;
573 		OUT_RING(dev_priv->dri1.front_offset);
574 		dev_priv->dri1.current_page = 0;
583 	master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
588 		OUT_RING(dev_priv->dri1.counter);
593 	master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
623 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
634 	if (!dev_priv->dri1.allow_batchbuffer) {
668 		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
679 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
735 		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
747 	drm_i915_private_t *dev_priv = dev->dev_private;
754 	dev_priv->dri1.counter++;
755 	if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
756 		dev_priv->dri1.counter = 1;
758 		master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
763 		OUT_RING(dev_priv->dri1.counter);
768 	return dev_priv->dri1.counter;
773 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
776 	struct intel_ring_buffer *ring = LP_RING(dev_priv);
779 		  READ_BREADCRUMB(dev_priv));
781 	if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
783 			master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
792 			    READ_BREADCRUMB(dev_priv) >= irq_nr);
794 	} else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
799 			  READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
810 	drm_i915_private_t *dev_priv = dev->dev_private;
817 	if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
841 	drm_i915_private_t *dev_priv = dev->dev_private;
847 	if (!dev_priv) {
858 	drm_i915_private_t *dev_priv = dev->dev_private;
864 	if (!dev_priv) {
919 	drm_i915_private_t *dev_priv = dev->dev_private;
923 	if (!dev_priv) {
933 		value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
936 		value = READ_BREADCRUMB(dev_priv);
945 		value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
948 		value = dev_priv->overlay ? 1 : 0;
958 		value = intel_ring_initialized(&dev_priv->ring[VCS]);
961 		value = intel_ring_initialized(&dev_priv->ring[BCS]);
964 		value = intel_ring_initialized(&dev_priv->ring[VECS]);
985 		value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1026 	drm_i915_private_t *dev_priv = dev->dev_private;
1029 	if (!dev_priv) {
1040 		dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1043 		if (param->value > dev_priv->num_fence_regs ||
1047 		dev_priv->fence_reg_start = param->value;
1061 	drm_i915_private_t *dev_priv = dev->dev_private;
1071 	if (!dev_priv) {
1083 	ring = LP_RING(dev_priv);
1086 	dev_priv->dri1.gfx_hws_cpu_addr.offset = (u_offset_t)dev->agp_aperbase + hws->addr;
1087 	dev_priv->dri1.gfx_hws_cpu_addr.size = 4*1024;
1088 	dev_priv->dri1.gfx_hws_cpu_addr.type = 0;
1089 	dev_priv->dri1.gfx_hws_cpu_addr.flags = 0;
1090 	dev_priv->dri1.gfx_hws_cpu_addr.mtrr = 0;
1092 	drm_core_ioremap(&dev_priv->dri1.gfx_hws_cpu_addr, dev);
1093 	if (dev_priv->dri1.gfx_hws_cpu_addr.handle == NULL) {
1101 	(void) memset(dev_priv->dri1.gfx_hws_cpu_addr.handle, 0, PAGE_SIZE);
1113 	struct drm_i915_private *dev_priv = dev->dev_private;
1116 	struct drm_i915_bridge_dev *bridge_dev = &dev_priv->bridge_dev;
1199 	struct drm_i915_private *dev_priv = dev->dev_private;
1236 		dev_priv->mm.suspended = 0;
1240 	if (dev_priv->fbcon_obj != NULL) {
1261 	if (dev_priv->fbcon_obj != NULL)
1265 	dev_priv->enable_hotplug_processing = true;
1270 	dev_priv->mm.suspended = 0;
1280 	drm_mm_takedown(&dev_priv->mm.gtt_space);
1343 	struct drm_i915_private *dev_priv = dev->dev_private;
1362 	struct drm_i915_private *dev_priv;
1380 	dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1381 	if (dev_priv == NULL)
1384 	dev->dev_private = (void *)dev_priv;
1385 	dev_priv->dev = dev;
1386 	dev_priv->info = info;
1388 	dev_priv->info = (struct intel_device_info *) flags;
1395 	dev_priv->regs = drm_alloc(sizeof (drm_local_map_t), DRM_MEM_MAPS);
1396 	dev_priv->regs->offset = base;
1397 	dev_priv->regs->size = size;
1398 	dev_priv->regs->type = _DRM_REGISTERS;
1399 	dev_priv->regs->flags = _DRM_REMOVABLE;
1400 	if (drm_ioremap(dev, dev_priv->regs)) {
1405 	DRM_DEBUG("mmio paddr=%lx, kvaddr=%p", dev_priv->regs->offset, dev_priv->regs->handle);
1421 	dev_priv->wq = create_workqueue(dev->devinfo, "i915");  
1422 	if (dev_priv->wq == NULL) {
1429 	dev_priv->other_wq = create_workqueue(dev->devinfo, "i915_other");
1430 	if (dev_priv->other_wq == NULL) {
1468 	spin_lock_init(&dev_priv->irq_lock);
1469 	spin_lock_init(&dev_priv->gpu_error.lock);
1470 	spin_lock_init(&dev_priv->rps.lock);
1471 	spin_lock_init(&dev_priv->dpio_lock);
1473 	spin_lock_init(&dev_priv->rps.hw_lock);
1474 	spin_lock_init(&dev_priv->modeset_restore_lock);
1476 	dev_priv->num_plane = 1;
1478 		dev_priv->num_plane = 2;
1487 	dev_priv->mm.suspended = 1;
1495 	dev_priv->gpu_hang = 0;
1497 	init_timer(&dev_priv->gpu_top_timer);
1498 	setup_timer(&dev_priv->gpu_top_timer, gpu_top_handler,
1502 		INIT_LIST_HEAD(&dev_priv->batch_list);
1507 	destroy_workqueue(dev_priv->other_wq);
1509 	destroy_workqueue(dev_priv->wq);
1511 	drm_ioremapfree(dev_priv->regs);
1514 	kfree(dev_priv, sizeof(struct drm_i915_private));
1520 	struct drm_i915_private *dev_priv = dev->dev_private;
1533 	destroy_workqueue(dev_priv->other_wq);
1534 	destroy_workqueue(dev_priv->wq);
1536 	del_timer_sync(&dev_priv->gpu_top_timer);
1537 	destroy_timer(&dev_priv->gpu_top_timer);
1538 	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1539 	destroy_timer(&dev_priv->gpu_error.hangcheck_timer);
1547 	if (dev_priv->gtt.total !=0) {
1560 		if (dev_priv->fbcon_obj != NULL)
1575 		if (dev_priv->gtt.scratch_page)
1577 		if (dev_priv->fbcon_obj != NULL) {
1578 			i915_gem_free_object(&dev_priv->fbcon_obj->base);
1579 			dev_priv->fbcon_obj = NULL;
1583 	drm_mm_takedown(&dev_priv->mm.gtt_space);
1584 	dev_priv->gtt.gtt_remove(dev);
1586 	if (dev_priv->regs != NULL)
1587 		(void) drm_rmmap(dev, dev_priv->regs);
1589 	mutex_destroy(&dev_priv->irq_lock);
1591 	pci_dev_put(dev_priv->bridge_dev);
1595 		list_for_each_entry_safe(r_list, list_temp, struct batch_info_list, &dev_priv->batch_list, head) {
1600 		list_del(&dev_priv->batch_list);
1612 	struct drm_i915_private *dev_priv = dev->dev_private;
1639 			pci_dev_put(dev_priv->bridge_dev);
1648 				pci_dev_put(dev_priv->bridge_dev);
1654 	dev_priv->isX = 1;
1696 	drm_i915_private_t *dev_priv = dev->dev_private;
1701 	if (!dev_priv)
1703 	dev_priv->isX = 0;
1722 	struct drm_i915_private *dev_priv = dev->dev_private;
1725 	if (dev_priv->fbcon_obj)
1729 	if (dev_priv->vt_holding > 0) {
1736 	dev_priv->vt_holding = 0;
1741 	drm_i915_private_t *dev_priv = dev->dev_private;
1743 	if (dev_priv->fbcon_obj)
1751 	dev_priv->vt_holding = 1;