Lines Matching refs:OUT_RING
53 #define OUT_RING(x) \
373 OUT_RING(buffer[i]);
375 OUT_RING(0);
402 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
403 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
404 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
405 OUT_RING(DR4);
411 OUT_RING(GFX_OP_DRAWRECT_INFO);
412 OUT_RING(DR1);
413 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
414 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
415 OUT_RING(DR4);
416 OUT_RING(0);
439 OUT_RING(MI_STORE_DWORD_INDEX);
440 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
441 OUT_RING(dev_priv->dri1.counter);
442 OUT_RING(0);
511 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
512 OUT_RING(batch->start);
514 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
515 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
522 OUT_RING(MI_BATCH_BUFFER);
523 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
524 OUT_RING(batch->start + batch->used - 4);
525 OUT_RING(0);
533 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
534 OUT_RING(MI_NOOP);
564 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
565 OUT_RING(0);
567 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
568 OUT_RING(0);
570 OUT_RING(dev_priv->dri1.back_offset);
573 OUT_RING(dev_priv->dri1.front_offset);
576 OUT_RING(0);
578 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
579 OUT_RING(0);
586 OUT_RING(MI_STORE_DWORD_INDEX);
587 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
588 OUT_RING(dev_priv->dri1.counter);
589 OUT_RING(0);
761 OUT_RING(MI_STORE_DWORD_INDEX);
762 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
763 OUT_RING(dev_priv->dri1.counter);
764 OUT_RING(MI_USER_INTERRUPT);