Cross Reference: /solaris-x11-s11/open-src/kernel/efb/src/radeon

Lines Matching refs:sarea_priv
762 	x += dev_priv->sarea_priv->boxes[0].x1;
763 	y += dev_priv->sarea_priv->boxes[0].y1;
862 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
864 	int nbox = sarea_priv->nbox;
865 	drm_clip_rect_t *pbox = sarea_priv->boxes;
900 		dev_priv->sarea_priv->ctx_owner = 0;
980 		dev_priv->sarea_priv->ctx_owner = 0;
1268 		dev_priv->sarea_priv->ctx_owner = 0;
1276 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1342 		dev_priv->sarea_priv->ctx_owner = 0;
1350 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1387 	dev_priv->sarea_priv->last_clear++;
1391 	RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
1400 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1401 	int nbox = sarea_priv->nbox;
1402 	drm_clip_rect_t *pbox = sarea_priv->boxes;
1463 	dev_priv->sarea_priv->last_frame ++;
1467 	RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1482 	    dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
1498 	    dev_priv->sarea_priv->crtc2_base + offset);
1507 	dev_priv->sarea_priv->last_frame ++;
1508 	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
1513 	RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1554 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1557 	int nbox = sarea_priv->nbox;
1574 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1601 	buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1651 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1658 	int nbox = sarea_priv->nbox;
1691 			radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
2215 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2241 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2242 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2245 	    sarea_priv->nbox * sizeof (depth_boxes[0])))
2274 	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
2322 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2328 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2329 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2332 	dev_priv->sarea_priv->ctx_owner = 0;
2343 	drm_radeon_sarea_t *sarea_priv;
2356 	sarea_priv = dev_priv->sarea_priv;
2394 		if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2396 			    &sarea_priv->context_state,
2397 			    sarea_priv->tex_state,
2398 			    sarea_priv->dirty)) {
2403 			sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2413 		prim.vc_format = dev_priv->sarea_priv->vc_format;
2431 	drm_radeon_sarea_t *sarea_priv;
2444 	sarea_priv = dev_priv->sarea_priv;
2490 	if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2492 		    &sarea_priv->context_state,
2493 		    sarea_priv->tex_state,
2494 		    sarea_priv->dirty)) {
2499 		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2513 	prim.vc_format = dev_priv->sarea_priv->vc_format;
2702 	drm_radeon_sarea_t *sarea_priv;
2716 	sarea_priv = dev_priv->sarea_priv;
2764 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2806 		if (sarea_priv->nbox == 1)
2807 			sarea_priv->nbox = 0;
3389 			dev_priv->sarea_priv->tiling_enabled = 0;
3394 			dev_priv->sarea_priv->tiling_enabled = 1;