Lines Matching refs:OUT_RING_REG
184 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
1024 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
1027 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
1029 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
1252 OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
1253 OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
1254 OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
1255 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1256 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
1258 OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
1259 OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
1260 OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
1261 OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
1262 OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
1263 OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
1264 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
1335 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1336 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
1337 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
1338 OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
1494 OUT_RING_REG(RADEON_CRTC_OFFSET,
1497 OUT_RING_REG(RADEON_CRTC2_OFFSET,
2906 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2932 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);