Cross Reference: /solaris-x11-s11/open-src/kernel/efb/src/radeon

Lines Matching defs:prim
1544 	unsigned int prim;
1551     drm_buf_t *buf, drm_radeon_tcl_prim_t *prim)
1555 	int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1556 	int numverts = (int)prim->numverts;
1562 	    prim->prim, prim->vc_format, prim->start,
1563 	    prim->finish, prim->numverts);
1565 	if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
1566 		DRM_ERROR("bad prim %x numverts %d\n",
1567 		    prim->prim, prim->numverts);
1583 		OUT_RING(prim->vc_format);
1584 		OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
1648     drm_buf_t *elt_buf, drm_radeon_tcl_prim_t *prim)
1652 	int offset = dev_priv->gart_buffers_offset + prim->offset;
1656 	int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1657 	int count = (prim->finish - start) / sizeof (u16);
1661 	    prim->prim, prim->vc_format, prim->start,
1662 	    prim->finish, prim->offset, prim->numverts);
1664 	if (bad_prim_vertex_nr(prim->prim, count)) {
1665 		DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
1669 	if (start >= prim->finish || (prim->start & 0x7)) {
1670 		DRM_ERROR("buffer prim %d\n", prim->prim);
1674 	dwords = (prim->finish - prim->start + 3) / sizeof (u32);
1677 	    elt_buf->offset + prim->start);
1681 	data[2] = prim->numverts;
1682 	data[3] = prim->vc_format;
1683 	data[4] = (prim->prim |
1694 		    prim->start, prim->finish);
2347 	drm_radeon_tcl_prim_t prim;
2368 	if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2369 		DRM_ERROR("buffer prim %d\n", vertex.prim);
2409 		prim.start = 0;
2410 		prim.finish = vertex.count;	/* unused */
2411 		prim.prim = vertex.prim;
2412 		prim.numverts = vertex.count;
2413 		prim.vc_format = dev_priv->sarea_priv->vc_format;
2415 		radeon_cp_dispatch_vertex(dev, buf, &prim);
2435 	drm_radeon_tcl_prim_t prim;
2456 	if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2457 		DRM_ERROR("buffer prim %d\n", elts.prim);
2508 	prim.start = elts.start;
2509 	prim.finish = elts.end;
2510 	prim.prim = elts.prim;
2511 	prim.offset = 0;	/* offset from start of dma buffers */
2512 	prim.numverts = RADEON_MAX_VB_VERTS;	/* duh */
2513 	prim.vc_format = dev_priv->sarea_priv->vc_format;
2515 	radeon_cp_dispatch_indices(dev, buf, &prim);
2730 		vertex.prim = (void *)(uintptr_t)vertex32.prim;
2768 		drm_radeon_prim_t prim;
2771 		if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof (prim)))
2774 		if (prim.stateidx != laststate) {
2778 			    &vertex.state[prim.stateidx], sizeof (state)))
2786 			laststate = prim.stateidx;
2789 		tclprim.start = prim.start;
2790 		tclprim.finish = prim.finish;
2791 		tclprim.prim = prim.prim;
2792 		tclprim.vc_format = prim.vc_format;
2794 		if (prim.prim & RADEON_PRIM_WALK_IND) {
2795 			tclprim.offset = prim.numverts * 64;
2800 			tclprim.numverts = prim.numverts;