Lines Matching defs:clear

859     drm_radeon_clear_t *clear, drm_radeon_clear_rect_t *depth_boxes)
866 unsigned int flags = clear->flags;
890 * 2D fill to clear the front or back buffer.
895 OUT_RING(clear->color_mask);
908 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
924 OUT_RING(clear->clear_color);
945 OUT_RING(clear->clear_color);
955 /* hyper z clear */
972 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
973 ((clear->depth_mask & 0xff) << 24);
988 * or actually 0x3fff?), need to take z clear
995 * which indicate clear (15,16,31,32, all zero)
997 * same clear mask can be used. That's very
999 * different clear mask and different number
1000 * of tiles to clear if hierz is enabled or not !?!
1005 * clear mask : chooses the clearing pattern.
1006 * rv250: could be used to clear only parts of macrotiles
1009 * not clear tile (or maybe one of the bits indicates if
1011 * clear tile 1,...,.
1016 * rv100: clearmask covers 2x8 4x1 tiles, but one clear
1045 * cache like r100, but just needs to clear the
1067 /* the number of tiles to clear */
1070 * clear mask :
1098 * directly address/clear 4x4
1101 * still need clear mask for
1106 /* the number of tiles to clear */
1109 * clear mask :
1132 /* the number of tiles to clear */
1135 * clear mask :
1145 /* TODO don't always clear all hi-level z tiles */
1156 * or actually 0x3fff?), need to take z clear value
1170 * We have to clear the depth and/or stencil buffers by
1235 tempRB3D_STENCILREFMASK = clear->depth_mask;
1313 rb3d_stencilrefmask = clear->depth_mask;
1383 * Increment the clear counter. The client-side 3D driver must
1384 * wait on this value before performing the clear ioctl. We
2216 drm_radeon_clear_t clear;
2226 clear.flags = clear32.flags;
2227 clear.clear_color = clear32.clear_color;
2228 clear.clear_depth = clear32.clear_depth;
2229 clear.color_mask = clear32.color_mask;
2230 clear.depth_mask = clear32.depth_mask;
2231 clear.depth_boxes = (void*)(uintptr_t)clear32.depth_boxes;
2234 DRM_COPYFROM_WITH_RETURN(&clear, (void *)data, sizeof (clear));
2244 if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes,
2248 radeon_cp_dispatch_clear(dev, &clear, depth_boxes);