Cross Reference: /solaris-x11-s11/open-src/kernel/efb/src/radeon

Lines Matching defs:dev_priv
43 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 mask)
74 	drm_radeon_private_t *dev_priv =
82 	stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
87 	stat &= dev_priv->irq_enable_reg;
91 		DRM_WAKEUP(&dev_priv->swi_queue);
96 		int vblank_crtc = dev_priv->vblank_crtc;
120 	drm_radeon_private_t *dev_priv = dev->dev_private;
124 	atomic_inc(&dev_priv->swi_emitted);
125 	ret = atomic_read(&dev_priv->swi_emitted);
138 	drm_radeon_private_t *dev_priv =
145 	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
147 	DRM_WAIT_ON(ret, &dev_priv->swi_queue, 3 * DRM_HZ,
156 	drm_radeon_private_t *dev_priv =
161 	if (!dev_priv) {
179 	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
216 	drm_radeon_private_t *dev_priv = dev->dev_private;
222 	if (!dev_priv) {
260 	drm_radeon_private_t *dev_priv = dev->dev_private;
263 	if (!dev_priv) {
275 	drm_radeon_private_t *dev_priv;
277 	dev_priv = (drm_radeon_private_t *)dev->dev_private;
278 	dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
280 	if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1) {
281 		dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
284 	if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2) {
285 		dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
288 	RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
289 	dev_priv->irq_enabled = 1;
299 	drm_radeon_private_t *dev_priv =
306 	(void) radeon_acknowledge_irqs(dev_priv,
314 	drm_radeon_private_t *dev_priv =
317 	atomic_set(&dev_priv->swi_emitted, 0);
318 	DRM_INIT_WAITQUEUE(&dev_priv->swi_queue, DRM_INTR_PRI(dev));
326 	drm_radeon_private_t *dev_priv =
328 	if (!dev_priv)
333 	DRM_FINI_WAITQUEUE(&dev_priv->swi_queue);
339 	drm_radeon_private_t *dev_priv;
343 	dev_priv = (drm_radeon_private_t *)dev->dev_private;
358 	drm_radeon_private_t *dev_priv;
360 	dev_priv = (drm_radeon_private_t *)dev->dev_private;
366 	dev_priv->vblank_crtc = (unsigned int)value;