Lines Matching defs:ctx
41 efb_context_t *ctx)
47 mi->next = ctx->mappings;
52 mi->ctx = ctx;
56 ctx->mappings = mi;
70 efb_context_t *ctx;
89 ctx = (efb_context_t *)(radeon_priv->private_data);
90 if (ctx == NULL) {
91 ctx = kmem_zalloc(sizeof (efb_context_t), KM_SLEEP);
92 ctx->mstate = mstate;
93 ctx->mappings = NULL;
94 ctx->md = radeon_priv;
95 ctx->next = NULL;
96 radeon_priv->private_data = (void *)ctx;
98 *pvtp = efb_new_mapping(mstate, dhp, off, len, ctx);
101 *pvtp = efb_new_mapping(mstate, dhp, off, len, ctx);
158 if (mi->ctx == NULL || mi->ctx == efb_priv->cur_ctx) {
186 efb_context_t *ctx;
200 ctx = mi->ctx;
205 rval = efb_ctx_make_current(efb_priv, ctx);
217 efb_ctx_save(efb_private_t *efb_priv, efb_context_t *ctx)
226 ctx->colormap[0][i] = efb_priv->colormap[stream][0][i];
227 ctx->colormap[1][i] = efb_priv->colormap[stream][1][i];
228 ctx->colormap[2][i] = efb_priv->colormap[stream][2][i];
231 ctx->default_pitch_offset = regr(DEFAULT_PITCH_OFFSET);
232 ctx->src_pitch_offset = regr(RADEON_SRC_PITCH_OFFSET);
233 ctx->dst_pitch_offset = regr(RADEON_DST_PITCH_OFFSET);
234 ctx->default_sc_bottom_right = regr(DEFAULT_SC_BOTTOM_RIGHT);
235 ctx->dp_gui_master_cntl = regr(RADEON_DP_GUI_MASTER_CNTL);
236 ctx->dst_line_start = regr(DST_LINE_START);
237 ctx->dst_line_end = regr(DST_LINE_END);
238 ctx->rb3d_cntl = regr(RB3D_CNTL);
239 ctx->dp_write_mask = regr(DP_WRITE_MSK);
240 ctx->dp_mix = regr(DP_MIX);
241 ctx->dp_datatype = regr(DP_DATATYPE);
242 ctx->dp_cntl = regr(DP_CNTL);
243 ctx->src_y = regr(SRC_Y);
244 ctx->src_x = regr(SRC_X);
245 ctx->dst_y = regr(DST_Y);
246 ctx->dst_x = regr(DST_X);
252 efb_ctx_restore(efb_private_t *efb_priv, efb_context_t *ctx)
260 efb_priv->colormap[stream][0][i] = ctx->colormap[0][i];
261 efb_priv->colormap[stream][1][i] = ctx->colormap[1][i];
262 efb_priv->colormap[stream][2][i] = ctx->colormap[2][i];
271 regw(DEFAULT_PITCH_OFFSET, ctx->default_pitch_offset);
272 regw(RADEON_DST_PITCH_OFFSET, ctx->dst_pitch_offset);
273 regw(RADEON_SRC_PITCH_OFFSET, ctx->src_pitch_offset);
274 regw(DEFAULT_SC_BOTTOM_RIGHT, ctx->default_sc_bottom_right);
275 regw(RADEON_DP_GUI_MASTER_CNTL, ctx->dp_gui_master_cntl);
276 regw(DST_LINE_START, ctx->dst_line_start);
277 regw(DST_LINE_END, ctx->dst_line_end);
278 regw(RB3D_CNTL, ctx->rb3d_cntl);
279 regw(DP_WRITE_MSK, ctx->dp_write_mask);
280 regw(DP_MIX, ctx->dp_mix);
281 regw(DP_DATATYPE, ctx->dp_datatype);
282 regw(DP_CNTL, ctx->dp_cntl);
283 regw(SRC_Y, ctx->src_y);
284 regw(SRC_X, ctx->src_x);
285 regw(DST_Y, ctx->dst_y);
286 regw(DST_X, ctx->dst_x);
299 efb_ctx_make_current(efb_private_t *efb_priv, efb_context_t *ctx)
303 if (efb_priv->cur_ctx == ctx)
334 if (ctx != NULL) {
335 efb_ctx_restore(efb_priv, ctx);
338 efb_priv->cur_ctx = ctx;
369 mi->ctx);
387 efb_context_t *ctx;
407 ctx = mi->ctx;
408 radeon_priv = ctx->md;
420 mi->off, off - mi->off, ctx);
426 mi->off + mi->len - (off+len), ctx);
432 else if (ctx != NULL)
433 ctx->mappings = mi->next;
439 if (ctx != NULL && ctx->mappings == NULL) {
444 if (ptr == ctx) {
445 radeon_priv->private_data = (void *)(ctx->next);
447 for (; ptr != NULL && ptr->next != ctx;
453 (void *)ctx);
455 ptr->next = ctx->next;
459 if (efb_priv->cur_ctx == ctx) {
462 kmem_free(ctx, sizeof (efb_context_t));
473 efb_ctx_unload_mappings(efb_context_t *ctx)
478 for (mi = ctx->mappings; mi != NULL; mi = mi->next) {
503 efb_context_t *ctx;
505 for (ctx = efb_priv->contexts; ctx != NULL; ctx = ctx->next) {
506 efb_ctx_unload_mappings(ctx);