Cross Reference: /osnet-11/usr/src/lib/libcfgadm/common/config

Lines Matching refs:minor
213     int (*fcn)(di_node_t node, di_minor_t minor, void *arg),
233 static int do_list_common(di_node_t node, di_minor_t minor, void *arg);
235 static int do_list_common_impl(di_node_t node, di_minor_t minor,
244 static cfga_err_t mklog_common(di_node_t node, di_minor_t minor,
247 static cfga_err_t null_mklog(di_node_t node, di_minor_t minor,
249 static cfga_err_t mklog_v1(di_node_t node, di_minor_t minor,
251 static cfga_err_t mklog_v2(di_node_t node, di_minor_t minor,
283 static char *get_class(di_minor_t minor);
1045 	di_minor_t minor,
1055 	di_minor_t minor,
1067 	return (mklog_common(node, minor, liblocp, len));
1087 	di_minor_t minor,
1114 	return (mklog_common(node, minor, liblocp, len));
1123 	di_minor_t minor,
1132 	minor_name = di_minor_name(minor);
1400 	 * NOTE that PCIE/PCISHPC connectors also have minor nodes &
1473 	di_minor_t minor,
1476 	return (load_lib_impl(node, minor, NULL, libloc_p));
1497 	di_minor_t minor,
1505 	if (minor != DI_MINOR_NIL && hp != DI_HP_NIL)
1508 	if (minor != DI_MINOR_NIL)
1509 		name = di_minor_name(minor);
1528 		if (minor != DI_MINOR_NIL) {
1529 			if (libp->vers_ops->mklog(node, minor, libp, libloc_p)
1569 	if (minor != DI_MINOR_NIL) {
1571 		    libp->vers_ops->mklog(node, minor, libp, libloc_p)
1624 	di_minor_t minor,
1640 	class = get_class(minor);
1919 	int (*fcn)(di_node_t node, di_minor_t minor, void *arg),
1949 	/* Remove minor name (if any) */
1957 	 * Since we create minor nodes & dev links for both all PCI/PCIE
1996 	 * Failed to find a matching hp node, try minor node.
2048 	di_minor_t minor,
2051 	return (check_ap_impl(node, minor, NULL, arg));
2077 	di_minor_t minor,
2093 	if (minor != DI_MINOR_NIL && hp != DI_HP_NIL)
2121 	if (minor != DI_MINOR_NIL)
2122 		node_minor = di_minor_name(minor);
2162 		if (minor != DI_MINOR_NIL) {
2163 			if (find_lib(node, minor, libloc_p) != CFGA_OK) {
2167 			if (load_lib(node, minor, libloc_p) != CFGA_OK) {
2196 	di_minor_t minor,
2199 	return (check_ap_phys_impl(node, minor, DI_HP_NIL, arg));
2224 	di_minor_t minor,
2233 	if (minor != DI_MINOR_NIL && hp != DI_HP_NIL)
2238 	if (minor != DI_MINOR_NIL)
2239 		minor_name = di_minor_name(minor);
2254 		if (minor != DI_MINOR_NIL) {
2255 			if (find_lib(node, minor, libloc_p) != CFGA_OK) {
2259 			if (load_lib(node, minor, libloc_p) != CFGA_OK) {
2500 	 * Walk all minor nodes
2574 	di_minor_t minor,
2581 	minor_name = di_minor_name(minor);
2584 	 * since PCIE/PCIHSHPC connectors have both hp nodes and minor nodes
2586 	 * during walking minor nodes.
2602 	return (do_list_common_impl(node, minor, NULL, arg));
2627 	di_minor_t minor,
2636 	if (minor != DI_MINOR_NIL && hp != DI_HP_NIL)
2645 	if (minor != DI_MINOR_NIL) {
2646 		ret = find_lib(node, minor, &lib_loc);
2661 	if (minor != DI_MINOR_NIL) {
2662 		ret = load_lib(node, minor, &lib_loc);
2679 		if (minor != DI_MINOR_NIL) {
3116 get_class(di_minor_t minor)
3122 	if (minor == DI_MINOR_NIL) {
3126 	cp = di_minor_nodetype(minor);