Lines Matching refs:data
86 * align dst on 64 byte boundary; for main data movement:
87 * prefetch src data to L2 cache; let HW prefetch move data to L1 cache
101 * unrolled loop to move data.
105 * align dst on 64 byte boundary; prefetch src data to L1 cache
162 /* on T4, prefetch 20 is a strong read prefetch to L1 and L2 data cache */
163 /* prefetch 20 can cause inst pipeline to delay if data is in memory */
164 /* prefetch 21 is a strong read prefetch to L2 data cache, not L1 data cache */
220 or %o1, %o3, %o3 ! align data
620 * and total data to move is less than MED_MAX bytes
699 * This option wins over standard large data move when
701 * to short data moves.