Cross Reference: /osnet-11/usr/src/grub/grub-0.97/netboot/tg3.c

Lines Matching refs:tg3_writephy
212 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
251 	err  = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr);
252 	err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
264 	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
266 	tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
278 	err = tg3_writephy(tp, MII_BMCR, phy_control);
330 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
332 		tg3_writephy(tp, 0x16, 0x0002);
335 			tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
338 		tg3_writephy(tp, 0x16, 0x0202);
344 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
346 		tg3_writephy(tp, 0x16, 0x0082);
352 		tg3_writephy(tp, 0x16, 0x0802);
371 				tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
372 				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
373 				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
390 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
392 		tg3_writephy(tp, 0x16, 0x0002);
394 			tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
395 		tg3_writephy(tp, 0x16, 0x0202);
421 		tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
424 		tg3_writephy(tp, MII_BMCR,
429 		tg3_writephy(tp, MII_TG3_CTRL,
434 		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
437 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
438 		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
449 	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
450 	tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
452 	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
453 	tg3_writephy(tp, 0x16, 0x0000);
455 	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
457 	tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
461 	tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
627 	tg3_writephy(tp, MII_ADVERTISE, new_adv);
644 		tg3_writephy(tp, MII_TG3_CTRL, new_adv);
646 		tg3_writephy(tp, MII_TG3_CTRL, 0);
649 	tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
659 	err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20);
684 	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
734 		tg3_writephy(tp, 0x15, 0x0a75);
735 		tg3_writephy(tp, 0x1c, 0x8c68);
736 		tg3_writephy(tp, 0x1c, 0x8d68);
737 		tg3_writephy(tp, 0x1c, 0x8c68);
744 	tg3_writephy(tp, MII_TG3_IMASK, ~0);
747 		tg3_writephy(tp, MII_TG3_EXT_CTRL,
750 		tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1218 		tg3_writephy(tp, 0x16, 0x8007);
1221 		tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1227 		tg3_writephy(tp, 0x10, 0x8411);
1230 		tg3_writephy(tp, 0x11, 0x0a10);
1232 		tg3_writephy(tp, 0x18, 0x00a0);
1233 		tg3_writephy(tp, 0x16, 0x41ff);
1236 		tg3_writephy(tp, 0x13, 0x0400);
1238 		tg3_writephy(tp, 0x13, 0x0000);
1240 		tg3_writephy(tp, 0x11, 0x0a50);
1242 		tg3_writephy(tp, 0x11, 0x0a10);
1250 		tg3_writephy(tp, 0x10, 0x8011);
2488 		err  = tg3_writephy(tp, MII_ADVERTISE,
2502 		err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl);
2503 		err |= tg3_writephy(tp, MII_BMCR,
2508 		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2509 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2514 		tg3_writephy(tp, 0x1c, 0x8d68);
2515 		tg3_writephy(tp, 0x1c, 0x8d68);