Lines Matching refs:val
98 static void tg3_write_indirect_reg32(uint32_t off, uint32_t val)
101 pci_write_config_dword(tg3.pdev, TG3PCI_REG_DATA, val);
104 #define tw32(reg,val) tg3_write_indirect_reg32((reg),(val))
105 #define tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tg3.regs + (reg))
106 #define tw16(reg,val) writew(((val) & 0xffff), tg3.regs + (reg))
107 #define tw8(reg,val) writeb(((val) & 0xff), tg3.regs + (reg))
112 static void tw32_carefully(uint32_t reg, uint32_t val)
114 tw32(reg, val);
119 static void tw32_mailbox2(uint32_t reg, uint32_t val)
121 tw32_mailbox(reg, val);
125 static void tg3_write_mem(uint32_t off, uint32_t val)
128 pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
134 static void tg3_read_mem(uint32_t off, uint32_t *val)
137 pci_read_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
172 static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val)
179 *val = 0xffffffff;
203 *val = frame_val & MI_COM_DATA_MASK;
212 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
223 frame_val |= (val & MI_COM_DATA_MASK);
248 static int tg3_writedsp(struct tg3 *tp, uint16_t addr, uint16_t val)
252 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
259 uint32_t val;
265 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
266 tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
581 struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex)
594 result = map[(val & MII_TG3_AUX_STAT_SPDMASK) >> 8];
1415 uint32_t val;
1432 val = tr32(ofs);
1433 val &= ~enable_bit;
1434 tw32(ofs, val);
1439 val = tr32(ofs);
1440 if ((val & enable_bit) == 0)
1515 uint32_t val;
1538 val = GRC_MISC_CFG_CORECLK_RESET;
1540 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
1541 tw32(GRC_MISC_CFG, val);
1548 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
1557 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
1560 val |= PCISTATE_RETRY_SAME_DMA;
1561 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
1566 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
1567 val &= ~PCIX_CAPS_RELAXED_ORDERING;
1568 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
1585 uint32_t val;
1589 val = tr32(GRC_RX_CPU_EVENT);
1590 val |= (1 << 14);
1591 tw32(GRC_RX_CPU_EVENT, val);
1604 uint32_t val;
1611 tg3_read_mem(NIC_SRAM_FIRMWARE_MBOX, &val);
1612 if (val == (uint32_t) ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1619 val);
1744 uint32_t val, rdmac_mode;
1794 val = tr32(TG3PCI_PCISTATE);
1795 val |= PCISTATE_RETRY_SAME_DMA;
1796 tw32(TG3PCI_PCISTATE, val);
2034 val = ( WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
2042 val |= WDMAC_MODE_RX_ACCEL;
2044 tw32_carefully(WDMAC_MODE, val);
2047 val = tr32(TG3PCI_X_CAPS);
2049 val &= PCIX_CAPS_BURST_MASK;
2050 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2052 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
2053 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2055 val |= (tp->split_mode_max_reqs <<
2058 tw32(TG3PCI_X_CAPS, val);
2247 struct tg3 *tp __unused, uint32_t offset, uint32_t *val)
2278 *val = tr32(GRC_EEPROM_DATA);
2282 static int tg3_nvram_read(struct tg3 *tp, uint32_t offset, uint32_t *val)
2287 return tg3_nvram_read_using_eeprom(tp, offset, val);
2325 *val = bswap_32(tr32(NVRAM_RDDATA));
2379 uint32_t val;
2396 tg3_read_mem(NIC_SRAM_DATA_SIG, &val);
2397 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
2575 unsigned char val = vpd_data[i];
2578 if (val == 0x82 || val == 0x91) {
2585 if (val != 0x90)