Lines Matching defs:tp
43 /* (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
143 static void tg3_disable_ints(struct tg3 *tp)
146 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
150 static void tg3_switch_clocks(struct tg3 *tp)
158 tp->pci_clock_ctrl = clock_ctrl;
160 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
172 static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val)
177 tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
207 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
212 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
217 tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
243 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
248 static int tg3_writedsp(struct tg3 *tp, uint16_t addr, uint16_t val)
251 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr);
252 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
257 static void tg3_phy_set_wirespeed(struct tg3 *tp)
261 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
264 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
265 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
266 tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
269 static int tg3_bmcr_reset(struct tg3 *tp)
278 err = tg3_writephy(tp, MII_BMCR, phy_control);
284 err = tg3_readphy(tp, MII_BMCR, &phy_control);
300 static int tg3_wait_macro_done(struct tg3 *tp)
307 tg3_readphy(tp, 0x16, &tmp32);
317 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
330 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
332 tg3_writephy(tp, 0x16, 0x0002);
335 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
338 tg3_writephy(tp, 0x16, 0x0202);
339 if (tg3_wait_macro_done(tp)) {
344 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
346 tg3_writephy(tp, 0x16, 0x0082);
347 if (tg3_wait_macro_done(tp)) {
352 tg3_writephy(tp, 0x16, 0x0802);
353 if (tg3_wait_macro_done(tp)) {
361 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);
362 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);
363 if (tg3_wait_macro_done(tp)) {
371 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
372 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
373 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
383 static int tg3_phy_reset_chanpat(struct tg3 *tp)
390 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
392 tg3_writephy(tp, 0x16, 0x0002);
394 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
395 tg3_writephy(tp, 0x16, 0x0202);
396 if (tg3_wait_macro_done(tp))
403 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
412 err = tg3_bmcr_reset(tp);
419 tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
421 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
424 tg3_writephy(tp, MII_BMCR,
428 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig);
429 tg3_writephy(tp, MII_TG3_CTRL,
434 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
437 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
438 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
440 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
445 err = tg3_phy_reset_chanpat(tp);
449 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
450 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
452 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
453 tg3_writephy(tp, 0x16, 0x0000);
455 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
457 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
459 tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
461 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
469 static int tg3_phy_reset(struct tg3 *tp)
474 err = tg3_readphy(tp, MII_BMSR, &phy_status);
475 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
479 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
480 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
481 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
482 err = tg3_phy_reset_5703_4_5(tp);
487 err = tg3_bmcr_reset(tp);
491 tg3_phy_set_wirespeed(tp);
495 static void tg3_set_power_state_0(struct tg3 *tp)
498 int pm = tp->pm_cap;
503 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
505 pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);
510 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
512 tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
519 static void tg3_link_report(struct tg3 *tp)
521 if (!tp->carrier_ok) {
525 (tp->link_config.active_speed == SPEED_1000 ?
527 (tp->link_config.active_speed == SPEED_100 ?
529 (tp->link_config.active_duplex == DUPLEX_FULL ?
531 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "TX" : "",
532 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "RX" : "",
533 (tp->tg3_flags & (TG3_FLAG_TX_PAUSE |TG3_FLAG_RX_PAUSE)) ? "flow control" : "");
537 #define tg3_link_report(tp)
540 static void tg3_setup_flow_control(struct tg3 *tp, uint32_t local_adv, uint32_t remote_adv)
565 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
566 tp->tg3_flags |= new_tg3_flags;
569 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
571 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
574 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
576 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
581 struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex)
599 static int tg3_phy_copper_begin(struct tg3 *tp)
603 tp->link_config.advertising =
609 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) {
610 tp->link_config.advertising &=
615 if (tp->link_config.advertising & ADVERTISED_10baseT_Half) {
618 if (tp->link_config.advertising & ADVERTISED_10baseT_Full) {
621 if (tp->link_config.advertising & ADVERTISED_100baseT_Half) {
624 if (tp->link_config.advertising & ADVERTISED_100baseT_Full) {
627 tg3_writephy(tp, MII_ADVERTISE, new_adv);
629 if (tp->link_config.advertising &
632 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) {
635 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) {
638 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
639 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
640 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
644 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
646 tg3_writephy(tp, MII_TG3_CTRL, 0);
649 tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
654 static int tg3_init_5401phy_dsp(struct tg3 *tp)
659 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20);
661 err |= tg3_writedsp(tp, 0x0012, 0x1804);
662 err |= tg3_writedsp(tp, 0x0013, 0x1204);
663 err |= tg3_writedsp(tp, 0x8006, 0x0132);
664 err |= tg3_writedsp(tp, 0x8006, 0x0232);
665 err |= tg3_writedsp(tp, 0x201f, 0x0a20);
672 static int tg3_setup_copper_phy(struct tg3 *tp)
681 tp->mi_mode = MAC_MI_MODE_BASE;
682 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
684 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
689 if ( ( (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
690 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
691 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)) &&
692 (tp->carrier_ok)) {
693 tg3_readphy(tp, MII_BMSR, &bmsr);
694 tg3_readphy(tp, MII_BMSR, &bmsr);
696 tg3_phy_reset(tp);
699 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
700 tg3_readphy(tp, MII_BMSR, &bmsr);
701 tg3_readphy(tp, MII_BMSR, &bmsr);
703 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
707 err = tg3_init_5401phy_dsp(tp);
711 tg3_readphy(tp, MII_BMSR, &bmsr);
714 tg3_readphy(tp, MII_BMSR, &bmsr);
721 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
723 tp->link_config.active_speed == SPEED_1000) {
724 err = tg3_phy_reset(tp);
726 err = tg3_init_5401phy_dsp(tp);
731 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
732 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
734 tg3_writephy(tp, 0x15, 0x0a75);
735 tg3_writephy(tp, 0x1c, 0x8c68);
736 tg3_writephy(tp, 0x1c, 0x8d68);
737 tg3_writephy(tp, 0x1c, 0x8c68);
741 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
742 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
744 tg3_writephy(tp, MII_TG3_IMASK, ~0);
746 if (tp->led_mode == led_mode_three_link)
747 tg3_writephy(tp, MII_TG3_EXT_CTRL,
750 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
754 tg3_readphy(tp, MII_BMSR, &bmsr);
755 tg3_readphy(tp, MII_BMSR, &bmsr);
760 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
763 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
768 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
769 &tp->link_config.active_speed,
770 &tp->link_config.active_duplex);
771 tg3_readphy(tp, MII_BMCR, &bmcr);
772 tg3_readphy(tp, MII_BMCR, &bmcr);
781 tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl);
792 (tp->link_config.active_duplex == DUPLEX_FULL)) {
795 tg3_readphy(tp, MII_ADVERTISE, &local_adv);
798 tg3_readphy(tp, MII_LPA, &remote_adv);
807 tg3_setup_flow_control(tp, local_adv, remote_adv);
814 tg3_phy_copper_begin(tp);
816 tg3_readphy(tp, MII_BMSR, &tmp);
817 tg3_readphy(tp, MII_BMSR, &tmp);
822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
824 if (tp->link_config.active_speed == SPEED_100 ||
825 tp->link_config.active_speed == SPEED_10)
826 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
828 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
832 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
833 if (tp->link_config.active_duplex == DUPLEX_HALF)
834 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
836 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
838 if ((tp->led_mode == led_mode_link10) ||
840 tp->link_config.active_speed == SPEED_10))
841 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
844 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
852 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
853 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
854 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
855 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
858 tw32_carefully(MAC_MODE, tp->mac_mode);
863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
865 tp->link_config.active_speed == SPEED_1000 &&
866 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
867 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
876 if (current_link_up != tp->carrier_ok) {
877 tp->carrier_ok = current_link_up;
878 tg3_link_report(tp);
952 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1031 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1032 tw32_carefully(MAC_MODE, tp->mac_mode);
1055 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1056 tw32_carefully(MAC_MODE, tp->mac_mode);
1070 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1071 tw32_carefully(MAC_MODE, tp->mac_mode);
1155 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1156 tw32_carefully(MAC_MODE, tp->mac_mode);
1196 static int tg3_setup_fiber_phy(struct tg3 *tp)
1205 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1207 orig_active_speed = tp->link_config.active_speed;
1208 orig_active_duplex = tp->link_config.active_duplex;
1210 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
1211 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
1212 tw32_carefully(MAC_MODE, tp->mac_mode);
1215 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
1218 tg3_writephy(tp, 0x16, 0x8007);
1221 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1227 tg3_writephy(tp, 0x10, 0x8411);
1230 tg3_writephy(tp, 0x11, 0x0a10);
1232 tg3_writephy(tp, 0x18, 0x00a0);
1233 tg3_writephy(tp, 0x16, 0x41ff);
1236 tg3_writephy(tp, 0x13, 0x0400);
1238 tg3_writephy(tp, 0x13, 0x0000);
1240 tg3_writephy(tp, 0x11, 0x0a50);
1242 tg3_writephy(tp, 0x11, 0x0a10);
1250 tg3_writephy(tp, 0x10, 0x8011);
1258 if (!(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) {
1269 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
1272 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
1278 status = tg3_fiber_aneg_smachine(tp, &aninfo);
1286 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1287 tw32_carefully(MAC_MODE, tp->mac_mode);
1302 tg3_setup_flow_control(tp, local_adv, remote_adv);
1304 tp->tg3_flags |=
1327 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1328 tw32_carefully(MAC_MODE, tp->mac_mode);
1330 tp->hw_status->status =
1332 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
1348 tp->link_config.active_speed = SPEED_1000;
1349 tp->link_config.active_duplex = DUPLEX_FULL;
1351 tp->link_config.active_speed = SPEED_INVALID;
1352 tp->link_config.active_duplex = DUPLEX_INVALID;
1355 if (current_link_up != tp->carrier_ok) {
1356 tp->carrier_ok = current_link_up;
1357 tg3_link_report(tp);
1360 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1363 orig_active_speed != tp->link_config.active_speed ||
1364 orig_active_duplex != tp->link_config.active_duplex)
1365 tg3_link_report(tp);
1369 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY);
1370 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
1371 tw32_carefully(MAC_MODE, tp->mac_mode);
1381 static int tg3_setup_phy(struct tg3 *tp)
1385 if (tp->phy_id == PHY_ID_SERDES) {
1386 err = tg3_setup_fiber_phy(tp);
1388 err = tg3_setup_copper_phy(tp);
1391 if (tp->link_config.active_speed == SPEED_1000 &&
1392 tp->link_config.active_duplex == DUPLEX_HALF)
1412 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit)
1417 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1453 static int tg3_abort_hw(struct tg3 *tp)
1457 tg3_disable_ints(tp);
1459 tp->rx_mode &= ~RX_MODE_ENABLE;
1460 tw32_carefully(MAC_RX_MODE, tp->rx_mode);
1462 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE);
1463 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE);
1464 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE);
1465 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE);
1466 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE);
1467 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE);
1469 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE);
1470 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE);
1471 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1472 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE);
1473 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
1474 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE);
1478 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
1479 tw32_carefully(MAC_MODE, tp->mac_mode);
1481 tp->tx_mode &= ~TX_MODE_ENABLE;
1482 tw32_carefully(MAC_TX_MODE, tp->tx_mode);
1495 err = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
1496 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE);
1497 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
1502 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
1503 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
1507 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
1513 static void tg3_chip_reset(struct tg3 *tp)
1517 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1522 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
1539 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
1548 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
1553 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
1554 tp->misc_host_ctrl);
1558 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1559 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
1561 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
1563 pci_restore_state(tp->pdev, tp->pci_cfg_state);
1566 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
1568 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
1572 if (((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0) &&
1573 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
1574 tp->pci_clock_ctrl |=
1576 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1579 tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
1582 static void tg3_stop_fw(struct tg3 *tp)
1584 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
1602 static int tg3_restart_fw(struct tg3 *tp, uint32_t state)
1617 !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1622 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1629 static int tg3_halt(struct tg3 *tp)
1631 tg3_stop_fw(tp);
1632 tg3_abort_hw(tp);
1633 tg3_chip_reset(tp);
1634 return tg3_restart_fw(tp, DRV_STATE_UNLOAD);
1637 static void __tg3_set_mac_addr(struct tg3 *tp)
1642 addr_high = ((tp->nic->node_addr[0] << 8) |
1643 tp->nic->node_addr[1]);
1644 addr_low = ((tp->nic->node_addr[2] << 24) |
1645 (tp->nic->node_addr[3] << 16) |
1646 (tp->nic->node_addr[4] << 8) |
1647 (tp->nic->node_addr[5] << 0));
1653 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
1654 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
1655 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)) {
1661 addr_high = (tp->nic->node_addr[0] +
1662 tp->nic->node_addr[1] +
1663 tp->nic->node_addr[2] +
1664 tp->nic->node_addr[3] +
1665 tp->nic->node_addr[4] +
1666 tp->nic->node_addr[5]) &
1671 static void tg3_set_bdinfo(struct tg3 *tp, uint32_t bdinfo_addr,
1684 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1690 static void tg3_init_rings(struct tg3 *tp)
1696 tp->rx_std = &tg3_bss.rx_std[0];
1697 tp->rx_rcb = &tg3_bss.rx_rcb[0];
1698 tp->tx_ring = &tg3_bss.tx_ring[0];
1699 tp->hw_status = &tg3_bss.hw_status;
1700 tp->hw_stats = &tg3_bss.hw_stats;
1701 tp->mac_mode = 0;
1718 rxd = &tp->rx_std[i];
1742 static int tg3_setup_hw(struct tg3 *tp)
1748 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
1753 tg3_disable_ints(tp);
1758 tg3_set_power_state_0(tp);
1760 tg3_switch_clocks(tp);
1767 tg3_stop_fw(tp);
1771 tg3_chip_reset(tp);
1773 tw32(GRC_MODE, tp->grc_mode); /* Redundant? */
1775 err = tg3_restart_fw(tp, DRV_STATE_START);
1779 if (tp->phy_id == PHY_ID_SERDES) {
1780 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
1782 tw32_carefully(MAC_MODE, tp->mac_mode);
1789 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
1790 tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1792 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1793 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
1804 tg3_init_rings(tp);
1807 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1819 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
1821 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
1825 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
1826 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1827 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
1830 tp->grc_mode |
1838 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1840 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
1847 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
1849 tp->bufmgr_config.mbuf_read_dma_low_water);
1851 tp->bufmgr_config.mbuf_mac_rx_low_water);
1853 tp->bufmgr_config.mbuf_high_water);
1856 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
1858 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
1860 tp->bufmgr_config.mbuf_high_water_jumbo);
1863 tp->bufmgr_config.dma_low_water);
1865 tp->bufmgr_config.dma_high_water);
1933 virt_to_bus(tp->rx_std));
1934 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1946 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1952 tp->tx_prod = 0;
1956 tg3_set_bdinfo(tp,
1958 virt_to_bus(tp->tx_ring),
1965 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1972 tp->rx_rcb_ptr = 0;
1975 tg3_set_bdinfo(tp,
1977 virt_to_bus(tp->rx_rcb),
1981 tp->rx_std_ptr = TG3_DEF_RX_RING_PENDING;
1983 tp->rx_std_ptr);
1988 __tg3_set_mac_addr(tp);
1998 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2000 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2001 if (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
2003 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2017 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
2019 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
2021 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
2022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
2023 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
2025 tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
2030 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2039 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
2041 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2046 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
2048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2051 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2054 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2055 val |= (tp->split_mode_max_reqs <<
2137 virt_to_bus(tp->hw_stats));
2139 virt_to_bus(tp->hw_status));
2140 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2145 tp->tx_mode = TX_MODE_ENABLE;
2146 tw32_carefully(MAC_TX_MODE, tp->tx_mode);
2148 tp->rx_mode = RX_MODE_ENABLE;
2149 tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2151 tp->mi_mode = MAC_MI_MODE_BASE;
2152 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2156 if (tp->phy_id == PHY_ID_SERDES) {
2159 tp->rx_mode |= RX_MODE_KEEP_VLAN_TAG; /* drop tagged vlan packets */
2160 tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2162 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
2171 err = tg3_setup_phy(tp);
2181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
2185 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
2214 static void tg3_nvram_init(struct tg3 *tp)
2227 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2228 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2231 tp->tg3_flags |= TG3_FLAG_NVRAM;
2234 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
2241 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
2247 struct tg3 *tp __unused, uint32_t offset, uint32_t *val)
2282 static int tg3_nvram_read(struct tg3 *tp, uint32_t offset, uint32_t *val)
2286 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2287 return tg3_nvram_read_using_eeprom(tp, offset, val);
2289 if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED)
2374 static int tg3_phy_probe(struct tg3 *tp)
2383 tp->phy_id = PHY_ID_INVALID;
2386 if ((subsys_id_to_phy_id[i].subsys_vendor == tp->subsystem_vendor) &&
2387 (subsys_id_to_phy_id[i].subsys_devid == tp->subsystem_device)) {
2388 tp->phy_id = subsys_id_to_phy_id[i].phy_id;
2401 tp->nic_sram_data_cfg = nic_cfg;
2435 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2436 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
2437 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) &&
2439 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
2443 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
2445 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
2453 err = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
2454 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
2463 tp->phy_id = hw_phy_id;
2469 if (tp->phy_id == PHY_ID_INVALID) {
2473 tp->phy_id = eeprom_phy_id;
2477 err = tg3_phy_reset(tp);
2481 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2482 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2488 err = tg3_writephy(tp, MII_ADVERTISE,
2499 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2502 err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl);
2503 err |= tg3_writephy(tp, MII_BMCR,
2507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2508 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2509 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2510 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
2513 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2514 tg3_writephy(tp, 0x1c, 0x8d68);
2515 tg3_writephy(tp, 0x1c, 0x8d68);
2519 tg3_phy_set_wirespeed(tp);
2521 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
2522 err = tg3_init_5401phy_dsp(tp);
2529 if (tp->phy_id == PHY_ID_SERDES) {
2530 tp->led_mode = led_mode_three_link;
2532 else if (tp->subsystem_vendor == PCI_VENDOR_ID_DELL) {
2533 tp->led_mode = led_mode_link10;
2535 tp->led_mode = led_mode_three_link;
2538 tp->led_mode = eeprom_led_mode;
2541 if (tp->phy_id == PHY_ID_SERDES)
2542 tp->link_config.advertising =
2547 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2548 tp->link_config.advertising &=
2556 static void tg3_read_partno(struct tg3 *tp)
2564 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
2600 memcpy(tp->board_part_number,
2614 memcpy(tp->board_part_number, "none", sizeof("none"));
2620 static int tg3_get_invariants(struct tg3 *tp)
2629 pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);
2630 pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);
2652 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
2656 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
2664 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg);
2666 tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT);
2669 tp->misc_host_ctrl |= (misc_ctrl_reg &
2671 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
2672 tp->misc_host_ctrl);
2674 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency);
2676 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64);
2679 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg);
2690 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
2700 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
2702 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
2705 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
2708 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
2712 tg3_set_power_state_0(tp);
2719 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
2720 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2721 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
2722 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) {
2723 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
2742 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2745 tw32(GRC_MODE, tp->grc_mode);
2747 tg3_switch_clocks(tp);
2757 tg3_nvram_init(tp);
2767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
2769 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
2770 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
2773 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
2776 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
2779 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) &&
2781 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2782 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM) &&
2783 ((tp->pdev->dev_id == PCI_DEVICE_ID_TIGON3_5901) ||
2784 (tp->pdev->dev_id == PCI_DEVICE_ID_TIGON3_5901_2)))) {
2785 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
2788 err = tg3_phy_probe(tp);
2793 tg3_read_partno(tp);
2811 static int tg3_get_device_address(struct tg3 *tp)
2813 struct nic *nic = tp->nic;
2816 if (PCI_FUNC(tp->pdev->devfn) == 0)
2834 else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
2835 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
2860 static int tg3_setup_dma(struct tg3 *tp)
2864 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
2865 tp->dma_rwctrl =
2871 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2872 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
2876 tp->dma_rwctrl =
2883 tp->dma_rwctrl =
2891 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2892 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2896 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
2901 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2902 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2903 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2906 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
2908 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
2913 static void tg3_init_link_config(struct tg3 *tp)
2915 tp->link_config.advertising =
2920 tp->carrier_ok = 0;
2921 tp->link_config.active_speed = SPEED_INVALID;
2922 tp->link_config.active_duplex = DUPLEX_INVALID;
2927 static const char * tg3_phy_string(struct tg3 *tp)
2929 switch (tp->phy_id & PHY_ID_MASK) {
2946 static void tg3_poll_link(struct tg3 *tp)
2951 if (tp->phy_id == PHY_ID_SERDES) {
2952 if (tp->carrier_ok?
2955 tw32_carefully(MAC_MODE, tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK);
2956 tw32_carefully(MAC_MODE, tp->mac_mode);
2958 tg3_setup_phy(tp);
2963 tg3_setup_phy(tp);
2971 static void tg3_ack_irqs(struct tg3 *tp)
2973 if (tp->hw_status->status & SD_STATUS_UPDATED) {
2988 tp->hw_status->status &= ~SD_STATUS_UPDATED;
2998 struct tg3 *tp = &tg3;
3003 if ( (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) && !retrieve )
3006 tg3_ack_irqs(tp);
3008 if (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) {
3011 desc = &tp->rx_rcb[tp->rx_rcb_ptr];
3019 tp->rx_rcb_ptr = (tp->rx_rcb_ptr + 1) % TG3_RX_RCB_RING_SIZE;
3022 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, tp->rx_rcb_ptr);
3026 tp->rx_std_ptr = (tp->rx_std_ptr + 1) % TG3_RX_RING_SIZE;
3027 tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tp->rx_std_ptr);
3030 tg3_poll_link(tp);
3038 static void tg3_set_txd(struct tg3 *tp, int entry,
3042 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3068 struct tg3 *tp;
3073 tp = &tg3;
3075 entry = tp->tx_prod;
3076 while((tp->hw_status->idx[0].tx_consumer != entry) &&
3077 (tp->hw_status->idx[0].tx_consumer != PREV_TX(entry))) {
3082 tg3_halt(tp);
3083 tg3_setup_hw(tp);
3099 txd = &tp->tx_ring[entry];
3112 tp->tx_prod = entry;
3120 struct tg3 *tp = &tg3;
3131 tg3_halt(tp);
3132 tp->tg3_flags &= ~(TG3_FLAG_INIT_COMPLETE|TG3_FLAG_GOT_SERDES_FLOWCTL);
3133 tp->carrier_ok = 0;
3134 iounmap((void *)tp->regs);
3159 struct tg3 *tp = &tg3;
3166 memset(tp, 0, sizeof(*tp));
3186 tp->pdev = pdev;
3187 tp->nic = nic;
3188 tp->pm_cap = pm_cap;
3189 tp->rx_mode = 0;
3190 tp->tx_mode = 0;
3191 tp->mi_mode = MAC_MI_MODE_BASE;
3192 tp->tg3_flags = 0 & ~TG3_FLAG_INIT_COMPLETE;
3198 tp->misc_host_ctrl =
3210 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
3213 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
3215 tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
3216 if (tp->regs == 0UL) {
3221 tg3_init_link_config(tp);
3223 err = tg3_get_invariants(tp);
3229 err = tg3_get_device_address(tp);
3236 tg3_setup_dma(tp);
3242 pci_save_state(tp->pdev, tp->pci_cfg_state);
3245 tp->board_part_number,
3246 tp->pci_chip_rev_id,
3247 tg3_phy_string(tp),
3248 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
3249 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
3250 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
3251 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
3252 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"));
3255 err = tg3_setup_hw(tp);
3259 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
3262 tg3_poll_link(tp);
3263 for(i = 0; !tp->carrier_ok && (i < VALID_LINK_TIMEOUT*100); i++) {
3265 tg3_poll_link(tp);
3267 if (!tp->carrier_ok){
3280 iounmap((void *)tp->regs);