Cross Reference: /osnet-11/usr/src/grub/grub-0.97/netboot/pci.h

Lines Matching refs:bus
28 #define PCI_COMMAND_MASTER		0x4	/* Enable bus mastering */
56 #define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
113 #define PCI_INTERRUPT_PIN	0x3d	/* IRQ pin on PCI bus (A-D) */
116 #define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
117 #define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
118 #define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
151 #define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
278 	unsigned char		bus;
286 extern int pcibios_read_config_byte(unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t *value);
287 extern int pcibios_write_config_byte (unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t value);
288 extern int pcibios_read_config_word(unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t *value);
289 extern int pcibios_write_config_word (unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t value);
290 extern int pcibios_read_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t *value);
291 extern int pcibios_write_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t value);
292 extern unsigned long pcibios_bus_base(unsigned int bus);
299 	return pcibios_read_config_byte(dev->bus, dev->devfn, where, value);
304 	return pcibios_write_config_byte(dev->bus, dev->devfn, where, value);
309 	return pcibios_read_config_word(dev->bus, dev->devfn, where, value);
314 	return pcibios_write_config_word(dev->bus, dev->devfn, where, value);
319 	return pcibios_read_config_dword(dev->bus, dev->devfn, where, value);
324 	return pcibios_write_config_dword(dev->bus, dev->devfn, where, value);