Lines Matching refs:outb
120 outb(src & 0xff, eth_asic_base + WD_GP2);
121 outb(src >> 8, eth_asic_base + WD_GP2);
123 outb(D8390_COMMAND_RD2 |
125 outb(cnt, eth_nic_base + D8390_P0_RBCR0);
126 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
127 outb(src, eth_nic_base + D8390_P0_RSAR0);
128 outb(src>>8, eth_nic_base + D8390_P0_RSAR1);
129 outb(D8390_COMMAND_RD0 |
133 outb(src & 0xff, eth_asic_base + _3COM_DALSB);
134 outb(src >> 8, eth_asic_base + _3COM_DAMSB);
135 outb(t503_output | _3COM_CR_START, eth_asic_base + _3COM_CR);
157 outb(t503_output, eth_asic_base + _3COM_CR);
170 outb(dst & 0xff, eth_asic_base + WD_GP2);
171 outb(dst >> 8, eth_asic_base + WD_GP2);
173 outb(D8390_COMMAND_RD2 |
175 outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR);
176 outb(cnt, eth_nic_base + D8390_P0_RBCR0);
177 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
178 outb(dst, eth_nic_base + D8390_P0_RSAR0);
179 outb(dst>>8, eth_nic_base + D8390_P0_RSAR1);
180 outb(D8390_COMMAND_RD1 |
184 outb(dst & 0xff, eth_asic_base + _3COM_DALSB);
185 outb(dst >> 8, eth_asic_base + _3COM_DAMSB);
187 outb(t503_output | _3COM_CR_DDIR | _3COM_CR_START, eth_asic_base + _3COM_CR);
206 outb(*(src++), eth_asic_base + ASIC_PIO);
210 outb(t503_output, eth_asic_base + _3COM_CR);
243 outb(4, eth_nic_base+D8390_P0_RCR);
244 outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, eth_nic_base + D8390_P0_COMMAND);
247 outb(mcfilter[i], eth_nic_base + 8 + i);
251 outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, eth_nic_base + D8390_P0_COMMAND);
252 outb(4 | 0x08, eth_nic_base+D8390_P0_RCR);
265 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
268 outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
271 outb(0x49, eth_nic_base+D8390_P0_DCR);
273 outb(0x48, eth_nic_base+D8390_P0_DCR);
274 outb(0, eth_nic_base+D8390_P0_RBCR0);
275 outb(0, eth_nic_base+D8390_P0_RBCR1);
276 outb(0x20, eth_nic_base+D8390_P0_RCR); /* monitor mode */
277 outb(2, eth_nic_base+D8390_P0_TCR);
278 outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
279 outb(eth_rx_start, eth_nic_base+D8390_P0_PSTART);
283 outb(0x10, eth_asic_base + 0x06); /* disable interrupts, enable PIO */
284 outb(0x01, eth_nic_base + 0x09); /* enable ring read auto-wrap */
286 outb(0, eth_nic_base + 0x09);
290 outb(eth_memsize, eth_nic_base+D8390_P0_PSTOP);
291 outb(eth_memsize - 1, eth_nic_base+D8390_P0_BOUND);
292 outb(0xFF, eth_nic_base+D8390_P0_ISR);
293 outb(0, eth_nic_base+D8390_P0_IMR);
296 outb(D8390_COMMAND_PS1 |
300 outb(D8390_COMMAND_PS1 |
303 outb(nic->node_addr[i], eth_nic_base+D8390_P1_PAR0+i);
305 outb(0xFF, eth_nic_base+D8390_P1_MAR0+i);
306 outb(eth_rx_start, eth_nic_base+D8390_P1_CURR);
309 outb(D8390_COMMAND_PS0 |
313 outb(D8390_COMMAND_PS0 |
315 outb(0xFF, eth_nic_base+D8390_P0_ISR);
316 outb(0, eth_nic_base+D8390_P0_TCR); /* transmitter on */
317 outb(4, eth_nic_base+D8390_P0_RCR); /* allow rx broadcast frames */
329 outb(t503_output, eth_asic_base + _3COM_CR);
345 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
348 outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
356 outb(0, eth_nic_base+D8390_P0_RBCR0); /* reset byte counter */
357 outb(0, eth_nic_base+D8390_P0_RBCR1);
365 outb(2, eth_nic_base+D8390_P0_TCR);
368 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
371 outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
379 outb(D8390_ISR_OVW, eth_nic_base+D8390_P0_ISR);
382 outb(0, eth_nic_base+D8390_P0_TCR);
413 outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
419 outb(WD_MSR_MENB, eth_asic_base + WD_MSR);
431 outb(0, eth_asic_base + WD_MSR);
461 outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
465 outb(D8390_COMMAND_PS0 |
469 outb(D8390_COMMAND_PS0 |
471 outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
472 outb(s, eth_nic_base+D8390_P0_TBCR0);
473 outb(s>>8, eth_nic_base+D8390_P0_TBCR1);
476 outb(D8390_COMMAND_PS0 |
480 outb(D8390_COMMAND_PS0 |
508 outb(D8390_COMMAND_PS1, eth_nic_base+D8390_P0_COMMAND);
510 outb(D8390_COMMAND_PS0, eth_nic_base+D8390_P0_COMMAND);
518 outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
523 outb(WD_MSR_MENB, eth_asic_base + WD_MSR);
566 outb(0, eth_asic_base + WD_MSR);
571 outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
579 outb(next-1, eth_nic_base+D8390_P0_BOUND);
684 outb(0x80, eth_asic_base + WD_MSR); /* Reset */
694 outb(0, eth_asic_base+WD_MSR);
697 outb(WD_MSR_MENB, eth_asic_base+WD_MSR);
698 outb((inb(eth_asic_base+0x04) |
700 outb(((unsigned)(eth_bmem >> 13) & 0x0F) |
703 outb((inb(eth_asic_base+0x04) &
708 outb(((unsigned)(eth_bmem >> 13) & 0x3F) | 0x40, eth_asic_base+WD_MSR);
713 outb(WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
715 outb((eth_laar =
812 outb(_3COM_CR_RST | _3COM_CR_XSEL, eth_asic_base + _3COM_CR );
813 outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR );
817 outb(_3COM_CR_EALO | _3COM_CR_XSEL, eth_asic_base + _3COM_CR);
829 outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR);
834 outb(_3COM_GACFR_RSEL |
837 outb(0xff, eth_asic_base + _3COM_VPTR2);
838 outb(0xff, eth_asic_base + _3COM_VPTR1);
839 outb(0x00, eth_asic_base + _3COM_VPTR0);
855 outb(eth_tx_start, eth_asic_base + _3COM_PSTR);
856 outb(eth_memsize, eth_asic_base + _3COM_PSPR);
885 outb(c, eth_asic_base + NE_RESET);
887 outb(D8390_COMMAND_STP |
889 outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR);
890 outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR);
891 outb(MEM_8192, eth_nic_base + D8390_P0_PSTART);
892 outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP);
905 outb(D8390_DCR_WTS |
907 outb(MEM_16384, eth_nic_base + D8390_P0_PSTART);
908 outb(MEM_32768, eth_nic_base + D8390_P0_PSTOP);