Cross Reference: /osnet-11/usr/src/grub/grub-0.97/netboot/ns8390.c

Lines Matching defs:eth_nic_base
41 static unsigned short	eth_nic_base, eth_asic_base;
124 		D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
125 	outb(cnt, eth_nic_base + D8390_P0_RBCR0);
126 	outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
127 	outb(src, eth_nic_base + D8390_P0_RSAR0);
128 	outb(src>>8, eth_nic_base + D8390_P0_RSAR1);
130 		D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
174 		D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
175 	outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR);
176 	outb(cnt, eth_nic_base + D8390_P0_RBCR0);
177 	outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
178 	outb(dst, eth_nic_base + D8390_P0_RSAR0);
179 	outb(dst>>8, eth_nic_base + D8390_P0_RSAR1);
181 		D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
215 		(inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC)
222 	while((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC)
238 static void enable_multicast(unsigned short eth_nic_base) 
243 	outb(4, eth_nic_base+D8390_P0_RCR);	
244 	outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, eth_nic_base + D8390_P0_COMMAND);
247 		outb(mcfilter[i], eth_nic_base + 8 + i);
248 		if(inb(eth_nic_base + 8 + i)!=mcfilter[i])
251 	outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, eth_nic_base + D8390_P0_COMMAND);
252 	outb(4 | 0x08, eth_nic_base+D8390_P0_RCR);
265 		outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
269 			D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
271 		outb(0x49, eth_nic_base+D8390_P0_DCR);
273 		outb(0x48, eth_nic_base+D8390_P0_DCR);
274 	outb(0, eth_nic_base+D8390_P0_RBCR0);
275 	outb(0, eth_nic_base+D8390_P0_RBCR1);
276 	outb(0x20, eth_nic_base+D8390_P0_RCR);	/* monitor mode */
277 	outb(2, eth_nic_base+D8390_P0_TCR);
278 	outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
279 	outb(eth_rx_start, eth_nic_base+D8390_P0_PSTART);
284 		outb(0x01, eth_nic_base + 0x09); /* enable ring read auto-wrap */
286 		outb(0, eth_nic_base + 0x09);
290 	outb(eth_memsize, eth_nic_base+D8390_P0_PSTOP);
291 	outb(eth_memsize - 1, eth_nic_base+D8390_P0_BOUND);
292 	outb(0xFF, eth_nic_base+D8390_P0_ISR);
293 	outb(0, eth_nic_base+D8390_P0_IMR);
297 			D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
301 			D8390_COMMAND_RD2 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
303 		outb(nic->node_addr[i], eth_nic_base+D8390_P1_PAR0+i);
305 		outb(0xFF, eth_nic_base+D8390_P1_MAR0+i);
306 	outb(eth_rx_start, eth_nic_base+D8390_P1_CURR);
310 			D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
314 			D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
315 	outb(0xFF, eth_nic_base+D8390_P0_ISR);
316 	outb(0, eth_nic_base+D8390_P0_TCR);	/* transmitter on */
317 	outb(4, eth_nic_base+D8390_P0_RCR);	/* allow rx broadcast frames */
319 	enable_multicast(eth_nic_base);
345 		outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
349 			D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
356 	outb(0, eth_nic_base+D8390_P0_RBCR0);	/* reset byte counter */
357 	outb(0, eth_nic_base+D8390_P0_RBCR1);
365 	outb(2, eth_nic_base+D8390_P0_TCR);
368 		outb(D8390_COMMAND_PS0 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
372 			D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
379 	outb(D8390_ISR_OVW, eth_nic_base+D8390_P0_ISR);
382 	outb(0, eth_nic_base+D8390_P0_TCR);
466 			D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
470 			D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
471 	outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
472 	outb(s, eth_nic_base+D8390_P0_TBCR0);
473 	outb(s>>8, eth_nic_base+D8390_P0_TBCR1);
477 			D8390_COMMAND_TXP | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
482 			D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
499 	if (!eth_drain_receiver && (inb(eth_nic_base+D8390_P0_ISR) & D8390_ISR_OVW)) {
504 	rstat = inb(eth_nic_base+D8390_P0_RSR);
506 	next = inb(eth_nic_base+D8390_P0_BOUND)+1;
508 	outb(D8390_COMMAND_PS1, eth_nic_base+D8390_P0_COMMAND);
509 	curr = inb(eth_nic_base+D8390_P1_CURR);
510 	outb(D8390_COMMAND_PS0, eth_nic_base+D8390_P0_COMMAND);
579 	outb(next-1, eth_nic_base+D8390_P0_BOUND);
651 	eth_nic_base = eth_asic_base + WD_NIC_ADDR;
653 	nic->ioaddr = eth_nic_base;
748 		for (idx = 0; (eth_nic_base = base[idx]) != 0; ++idx) {
750 			eth_asic_base = eth_nic_base + _3COM_ASIC_OFFSET;
818 		nic->ioaddr = eth_nic_base;
819                 printf("\n3Com 3c503 base %#hx, ", eth_nic_base);
825                         nic->node_addr[i] = inb(eth_nic_base+i);
878 		for (idx = 0; (eth_nic_base = probe_addrs[idx]) != 0; ++idx) {
880 			eth_asic_base = eth_nic_base + NE_ASIC_OFFSET;
888 				D8390_COMMAND_RD2, eth_nic_base + D8390_P0_COMMAND);
889 			outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR);
890 			outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR);
891 			outb(MEM_8192, eth_nic_base + D8390_P0_PSTART);
892 			outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP);
906 				D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR);
907 			outb(MEM_16384, eth_nic_base + D8390_P0_PSTART);
908 			outb(MEM_32768, eth_nic_base + D8390_P0_PSTOP);
914 		if (eth_nic_base == 0)
916 		if (eth_nic_base > ISA_MAX_ADDR)	/* PCI probably */
923 		nic->ioaddr = eth_nic_base;
925 			(eth_flags & FLAG_16BIT) ? '2' : '1', eth_nic_base,