Lines Matching refs:writel
400 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
405 writel(reg & ~NVREG_ADAPTCTL_RUNNING,
410 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
417 writel(value, base + NvRegMIIData);
420 writel(reg, base + NvRegMIIControl);
445 writel(reg | NVREG_ADAPTCTL_RUNNING,
458 writel(0, base + NvRegReceiverControl);
461 writel(np->linkspeed, base + NvRegLinkSpeed);
463 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
472 writel(0, base + NvRegReceiverControl);
478 writel(0, base + NvRegLinkSpeed);
486 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
495 writel(0, base + NvRegTransmitterControl);
501 writel(0, base + NvRegUnknownTransmitterReg);
510 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET,
514 writel(NVREG_TXRXCTL_BIT2, base + NvRegTxRxControl);
625 writel(addr[0], base + NvRegMulticastAddrA);
626 writel(addr[1], base + NvRegMulticastAddrB);
627 writel(mask[0], base + NvRegMulticastMaskA);
628 writel(mask[1], base + NvRegMulticastMaskB);
629 writel(pff, base + NvRegPacketFilterFlags);
645 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
646 writel(0, base + NvRegMulticastAddrB);
647 writel(0, base + NvRegMulticastMaskA);
648 writel(0, base + NvRegMulticastMaskB);
649 writel(0, base + NvRegPacketFilterFlags);
650 writel(0, base + NvRegAdapterControl);
651 writel(0, base + NvRegLinkSpeed);
652 writel(0, base + NvRegUnknownTransmitterReg);
654 writel(0, base + NvRegUnknownSetupReg6);
670 writel(mac[0], base + NvRegMacAddrA);
671 writel(mac[1], base + NvRegMacAddrB);
677 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
678 writel(0, base + NvRegTxRxControl);
680 writel(NVREG_TXRXCTL_BIT1, base + NvRegTxRxControl);
686 writel(0, base + NvRegUnknownSetupReg4);
689 writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed);
717 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
719 writel(readl(base + NvRegTransmitterStatus),
721 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
722 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
724 writel(readl(base + NvRegReceiverStatus),
729 writel(NVREG_RNDSEED_FORCE | (i & NVREG_RNDSEED_MASK),
731 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
732 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
733 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
734 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
735 writel((np->
738 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
739 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
742 writel((u32) virt_to_le32desc(&rx_ring[0]),
744 writel((u32) virt_to_le32desc(&tx_ring[0]),
748 writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) +
754 writel(NVREG_POWERSTATE_POWEREDUP | i,
759 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID,
761 writel(NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
763 writel(0, base + NvRegIrqMask);
765 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
767 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
768 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
771 writel(np->irqmask, base + NvRegIrqMask);
773 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
774 writel(0, base + NvRegMulticastAddrB);
775 writel(0, base + NvRegMulticastMaskA);
776 writel(0, base + NvRegMulticastMaskB);
777 writel(NVREG_PFF_ALWAYS | NVREG_PFF_MYADDR,
869 writel(NVREG_TXRXCTL_KICK, base + NvRegTxRxControl);
896 writel(0, base + NvRegIrqMask);
903 writel(np->orig_mac[0], base + NvRegMacAddrA);
904 writel(np->orig_mac[1], base + NvRegMacAddrB);