16  * 2 along with this work; if not, write to the Free Software Foundation,
59 // Convert Nodes to instruction bits and pass off to the VM
64   // The number of new nodes (mostly MachNop) is proportional to
108     // checking for _method means that OptoBreakpoint does not apply to
167   // Determine if we need to generate a stack overflow check.
175   // Determine if we need to generate a register stack overflow check.
185 // In order to catch compiler oop-map bugs, we have implemented
187 // This mode causes the compiler to insert a call to a runtime routine,
193 // (by zapping them to an invalid address).
212     warning("about to compile last zap");
222   // Insert call to zap runtime stub before every node with an oop map
230       // to allocation.  Calls to allocation passes in the old top-of-eden pointer
231       // and expect the C code to reset it.  Hence, there can be no safepoints between
232       // the inlined-allocation and the call to new_Java, etc.
234       // during the call to Zap, which also wants to grab the microlock.
271   // We need to copy the OopMap from the site we're zapping at.
272   // We have to make a copy, because the zap site might not be
276   // Add the cloned OopMap to the zap node
283   // This code duplicates the logic prior to the call of add_safepoint
293 // of a loop. When aligning a loop we need to provide enough instructions
294 // in cpu's fetch buffer to feed decoders. The loop alignment could be
296 // By default, the size is set to 999999 by Block's constructor so that
303   // The next condition is used to gate the loop alignment optimization.
306   // is equal to OptoLoopAlignment-1 except on new Intel cpus, where it is
307   // equal to 11 bytes which is the largest address NOP instruction.
353   // Initialize the sizes to 0
372     // During short branch replacement, we store the relative (to blk_starts)
374     // This is so that we do not need to recompute sizes of all nodes when
382     // Sum all instruction sizes to compute block size
404           // nop to disambiguate the two safepoints.
412           // Nop is inserted between "avoid back to back" instructions.
570   // Adjust reloc_size to number of record of relocation info
571   // Min is 2 bytes, max is probably 6 or 8, with a tax up to 25% for
578 // Create a bit of debug info and append it to the array.  The mapping is from
579 // Java local or expression stack to constant, register or stack-slot.  For
580 // doubles, insert 2 mappings and return 1 (to tell the caller that the next
659     // Normally, the allocation of high and low words to these registers
665     // is written to the lower memory address.  This may seem like
667     // the author of the <arch>.ad file to ensure that, for every
668     // even/odd double-register pair to which a double may be allocated,
669     // the word in the even single-register is stored to the first
671     // arbitrary, and are not tied to any machine-level encodings.)
687       // For SPARC we have to swap high and low words for
700       // were to grow upwards, the embedded doubles would be word-swapped.)
747     // Must be restored to the full-width 64-bit stack slot.
770     // were to grow upwards, the embedded doubles would be word-swapped.)
789     // were to grow upwards, the embedded doubles would be word-swapped.)
850   // Loop over the JVMState list to add scope information
857   // arrays) to descriptions of the object state.
860   // Visit scopes from oldest to youngest.
866     // to support GC; these do not support deoptimization.
947     // Build first class objects to pass to scope
967 // A simplified version of Process_OopMap_Node, to handle non-safepoints.
1036   // Visit scopes from oldest to youngest.
1055     C->record_failure("excessive request to CodeCache");
1074   // Sometimes we need to patch in a jump after the last instruction,
1089     // doesn't work if the fp reg to spill contains a single-precision denorm.
1092     // space here for the fp arg regs (f8-f15) we're going to thusly spill.
1121     // constant table (including the padding to the next section).
1126   // Initialize the space for the BufferBlob used to find and verify
1183   // of a loop. It is used to determine the padding for loop alignment.
1245     // If this block needs to start aligned (i.e, can be reached other
1293       // should be factored out.  Or maybe dispersed to the nodes?
1309         // could be moved to delay slot.
1320           // Avoid back to back some instructions.
1360               // Write the oopmap directly to the code blob??!!
1373         // If this is a null check, then add the start of the previous instruction to the list
1383           // Try to replace long branch if delay slot is not used,
1462             // edges have been added to the storeCMNode.
1472           // Intel all the time, with add-to-memory kind of opcodes.
1505       // in which case we'll need a pad to make the PcDesc sites unique
1508       // This is a small price to pay.
1515         // Avoid back to back some instructions.
1537             // Write the oopmap directly to the code blob??!!
1561     // If the next block is the top of a loop, pad this block out to align
1646       // This output goes directly to the tty, not the compiler log.
1647       // To enable tools to match it up with the compilation activity,
1648       // be sure to tag this tty output with the compile ID.
1714               // p leads to an exception handler (and is not fall through)
1726         // Note:  Due to empty block removal, one block may have
1885 // from first to last, and compute the latency of the instruction based
1896     // This is a kludge, forcing all latency calculations to start at 1.
1897     // Used to allow latency 0 to force an instruction to the beginning
1971   // Don't allow non-machine nodes to be handled this way
2082       // Recalculate position, moving to front of same latency
2104       def = def->in(0);         // propagate usage thru to the base instruction
2141   // Check for instructions to be placed in the delay slot. We
2155     // copied to the delay slot, and the branch goes to
2183             // A node that fits in the delay slot was found, so we need to
2186             // attempt to add this instruction to the bundle, we will skip
2204     // No delay slot, add a nop to the usage
2302   // It's possible to have a BoxLock in the graph and in the _bbs mapping but
2341 // the available list to the set of instructions that have no uses within this
2361   // Force the _uses count to never go to zero for unscheduable pieces
2466       break;                    // Funny loop structure to be sure...
2497       // Set _bb_end to point after last schedulable inst.
2532     // Now copy the instructions (in reverse order) back to the block
2572 // Check for edge existence.  Used to avoid adding redundant precedence edges.
2573 static bool edge_from_to( Node *from, Node *to ) {
2575     if( from->in(i) == to )
2600   // Zap to something reasonable for the verify code
2603   // Walk over the block backwards.  Check to make sure each DEF doesn't
2604   // kill a live value (other than the one it's supposed to).  Add each
2605   // USE to the live set.
2641   // Zap to something reasonable for the Antidependence code
2647 static void add_prec_edge_from_to( Node *from, Node *to ) {
2652   if( from != to &&             // No cycles (for things like LD L0,[L0+4] )
2653       !edge_from_to( from, to ) ) // Avoid duplicate edge
2654     from->add_prec(to);
2669   Node *kill = def;             // Rename 'def' to more descriptive 'kill'
2683       pinch = new (_cfg->C) Node(1); // Pinch point to-be
2694       add_prec_edge_from_to(later_def,pinch); // Add edge from kill to pinch
2703   // Add output-dependence edge from later def to kill
2705     add_prec_edge_from_to(later_def,kill); // Add edge from def to kill
2707   // See if current kill is also a use, and so is forced to be the pinch-point.
2723   // Add edge from kill to pinch-point
2734       // Use has to be block-local as well
2738       pinch->del_req(0);        // yank pointer to later-def, also set flag
2750 // allocated registers to prevent illegal code motion. Hopefully, the
2760   // of: a def, then some uses (connected to the def by true dependencies),
2762   // def.  The uses are allowed to float relative to each other, as are the
2763   // kills.  No use is allowed to slide past a kill (or def).  This requires
2765   // follow, up to the next def.  More edges are redundant, because later defs
2774   // For each DEF/KILL, we check to see if there's a prior DEF/KILL for this
2776   // register-to-def mapping.  If there is a prior DEF/KILL, we insert a
2778   // We put edges from the prior and current DEF/KILLs to the pinch point.
2780   // we merely add an edge from the current DEF/KILL to the pinch point.
2783   // put an edge from the pinch point to the USE.
2797     int is_def = n->outcnt();   // def if some uses prior to adding precedence edges
2800       // This can add edges to 'n' and obscure whether or not it was a def,
2815     // Kill projections on a branch should appear to occur on the
2842     // Do not allow defs of new derived values to float above GC
2847     // Add precedence edge from following safepoint to use of derived pointer
2860     if( n->jvms() ) {           // Precedence edge from derived to safept
2888 // 2 or more Calls.  A pinch node is used to prevent a
2971   tty->print("Nops added %d bytes to total of %d bytes",

Indexes created Tue Jul 24 14:28:13 CEST 2018