Lines Matching refs:Pipeline
1248 if (Pipeline::requires_bundling() && starts_bundle(head))
1280 assert(n->size(_regalloc) == Pipeline::instr_unit_size(), "delay slot instruction wrong size");
1288 if (Pipeline::requires_bundling() && starts_bundle(n))
1524 cb->set_insts_end(cb->insts_end() - Pipeline::instr_unit_size());
1545 int adjusted_offset = current_offset - Pipeline::instr_unit_size();
1750 uint Scheduling::_total_instructions_per_bundle[Pipeline::_max_instrs_per_cycle+1];
1954 const Pipeline *node_pipeline = n->pipeline();
1962 if (_bundle_instr_count + instruction_count > Pipeline::_max_instrs_per_cycle) {
1966 n->_idx, _bundle_instr_count + instruction_count, Pipeline::_max_instrs_per_cycle);
2018 if (_bundle_instr_count < Pipeline::_max_instrs_per_cycle) {
2138 const Pipeline *node_pipeline = n->pipeline();
2144 if (Pipeline::_branch_has_delay_slot &&
2170 const Pipeline *avail_pipeline = d->pipeline();
2177 Pipeline::instr_has_unit_size() &&
2178 d->size(_regalloc) == Pipeline::instr_unit_size() &&
2273 else if (instruction_count + _bundle_instr_count > Pipeline::_max_instrs_per_cycle) {
2278 Pipeline::_max_instrs_per_cycle);
2979 if (Pipeline::_branch_has_delay_slot) {
2990 for (uint i = 1; i <= Pipeline::_max_instrs_per_cycle; i++) {