Lines Matching defs:lrg
336 compact(); // Compact LRGs; return new lower max lrg
399 compact(); // Compact LRGs; return new lower max lrg
486 LRG &lrg = lrgs(_names[i]);
487 if (!lrg.alive()) {
489 } else if (lrg.num_regs() == 1) {
490 set1(i, lrg.reg());
492 if (!lrg._fat_proj) { // Must be aligned adjacent register set
495 OptoReg::Name hi = lrg.reg(); // Get hi register
496 OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo
506 OptoReg::Name hi = lrg.reg(); // Get hi register
507 lrg.Remove(hi); // Yank from mask
508 int lo = lrg.mask().find_first_elem(); // Find lo
512 if( lrg._is_oop ) _node_oops.set(i);
570 LRG &lrg = lrgs(vreg);
575 lrg._has_copy = 1;
585 lrg._is_float = 1;
591 lrg._was_spilled1 = 1;
593 lrg._was_spilled2 = 1;
597 if (trace_spilling() && lrg._def != NULL) {
599 if (lrg._defs == NULL) {
600 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
601 lrg._defs->append(lrg._def);
603 lrg._defs->append(n);
610 lrg._def = lrg._def ? NodeSentinel : n;
614 lrg.AND( rm );
624 lrg._is_vector = 1;
625 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD,
629 const RegMask &lrgmask = lrg.mask();
631 lrg._is_bound = 1;
634 if (lrg._maxfreq < b->_freq)
635 lrg._maxfreq = b->_freq;
642 lrg.set_num_regs(rm.Size());
643 lrg.set_reg_pressure(lrg.num_regs());
644 lrg._fat_proj = 1;
645 lrg._is_bound = 1;
649 lrg.set_num_regs(2); // Size is 2 stack words
651 lrg.set_num_regs(1); // Size is 1 stack word
687 lrg.set_reg_pressure(2); // use for v9 as well
689 lrg.set_reg_pressure(1); // normally one value per register
692 lrg._is_oop = 1;
697 lrg.set_num_regs(2);
700 lrg.set_reg_pressure(2);
703 lrg.set_reg_pressure(2);
705 lrg.set_reg_pressure(1);
708 lrg.set_reg_pressure(1); // normally one value per register
716 lrg._fat_proj = 1;
717 lrg._is_bound = 1;
725 lrg.set_num_regs(1);
727 lrg.set_reg_pressure(2);
729 lrg.set_reg_pressure(1);
735 lrg.set_num_regs(RegMask::SlotsPerVecS);
736 lrg.set_reg_pressure(1);
742 lrg.set_num_regs(RegMask::SlotsPerVecD);
743 lrg.set_reg_pressure(1);
749 lrg.set_num_regs(RegMask::SlotsPerVecX);
750 lrg.set_reg_pressure(1);
756 lrg.set_num_regs(RegMask::SlotsPerVecY);
757 lrg.set_reg_pressure(1);
791 LRG &lrg = lrgs(vreg);
814 lrg.AND( rm );
818 const RegMask &lrgmask = lrg.mask();
825 lrg._is_bound = 1;
834 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
835 assert(!lrg._fat_proj, "sanity");
836 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
839 if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) {
840 lrg._fat_proj = 1;
841 lrg._is_bound = 1;
846 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
848 lrg.Clear();
852 if( lrg._maxfreq < b->_freq )
853 lrg._maxfreq = b->_freq;
861 LRG &lrg = lrgs(i2);
862 assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
863 if (lrg.num_regs() > 1 && !lrg._fat_proj) {
864 lrg.clear_to_sets();
866 lrg.compute_set_mask_size();
867 if (lrg.not_free()) { // Handle case where we lose from the start
868 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
869 lrg._direct_conflict = 1;
871 lrg.set_degree(0); // no neighbors in IFG yet
917 LRG &lrg = lrgs(i);
921 if( lrg.lo_degree() ||
922 !lrg.alive() ||
923 lrg._must_spill ) {
929 OptoReg::Name hi_reg = lrg.mask().find_last_elem();
931 lrg._next = _lo_stk_degree;
934 lrg._next = _lo_degree;
939 lrg._next = _hi_degree;
940 lrg._prev = 0;
1135 // Is 'reg' register legal for 'lrg'?
1136 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) {
1138 lrg.mask().Member(OptoReg::add(reg,-chunk))) {
1146 // The 'lrg' already has cleared-to-set register mask (done in Select()
1149 // 'lrg' set size.
1150 // For set size 1 any register which is member of 'lrg' mask is legal.
1151 if (lrg.num_regs()==1)
1154 int mask = lrg.num_regs()-1;
1163 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1166 uint risk_lrg = Find(lrg._risk_bias);
1177 if (is_legal_reg(lrg, reg, chunk))
1182 uint copy_lrg = Find(lrg._copy_bias);
1188 if (is_legal_reg(lrg, reg, chunk))
1192 RegMask tempmask = lrg.mask();
1194 tempmask.clear_to_sets(lrg.num_regs());
1195 OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs());
1202 if (lrg._is_vector || lrg.num_regs() == 2) {
1204 return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk);
1210 OptoReg::Name reg = lrg.mask().find_first_elem();
1214 lrg.Remove(reg);
1215 OptoReg::Name reg2 = lrg.mask().find_first_elem();
1216 lrg.Insert(reg);
1225 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
1226 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
1227 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
1229 if( lrg.num_regs() == 1 || // Common Case
1230 !lrg._fat_proj ) // Aligned+adjacent pairs ok
1232 return bias_color(lrg, chunk);
1234 assert(!lrg._is_vector, "should be not vector here" );
1235 assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
1238 assert(lrg.compute_mask_size() == lrg.num_regs() ||
1239 lrg.num_regs() == 2,"fat projs exactly color" );
1242 return lrg.mask().find_last_elem();
1256 LRG *lrg = &lrgs(lidx);
1257 _simplified = lrg->_next;
1263 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
1264 lrg->degrees_of_freedom());
1265 lrg->dump();
1271 if( !lrg->alive() ) continue;
1273 const int is_allstack = lrg->mask().is_AllStack();
1286 debug_only(RegMask orig_mask = lrg->mask();)
1293 // will be a no-op. (Later on, if lrg runs out of possible colors in
1301 uint size = lrg->mask().Size();
1302 RegMask rm = lrg->mask();
1304 lrg->SUBTRACT(nlrg.mask());
1306 if (trace_spilling() && lrg->mask().Size() != size) {
1313 rm.SUBTRACT(lrg->mask());
1316 lrg->mask().dump();
1322 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1324 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1325 if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
1326 lrg->clear_to_sets();
1330 OptoReg::Name reg = choose_color( *lrg, chunk );
1332 debug_only(lrg->compute_set_mask_size());
1333 assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1342 lrg->Set_All();
1351 RegMask avail_rm = lrg->mask();
1355 lrg->set_reg(reg);
1365 int n_regs = lrg->num_regs();
1366 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1367 if (n_regs == 1 || !lrg->_fat_proj) {
1368 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity");
1369 lrg->Clear(); // Clear the mask
1370 lrg->Insert(reg); // Set regmask to match selected reg
1373 lrg->Insert(OptoReg::add(reg,-i));
1374 lrg->set_mask_size(n_regs);
1382 lrg->mask().dump();
1394 assert( lrg->alive(), "" );
1395 assert( !lrg->_fat_proj || lrg->is_multidef() ||
1396 lrg->_def->outcnt() > 0, "fat_proj cannot spill");
1400 lrg->set_reg(OptoReg::Name(spill_reg++));