Lines Matching +defs:val +defs:src
634 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
635 assert(src->is_constant(), "should not call otherwise");
637 LIR_Const* c = src->as_constant_ptr();
721 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
722 assert(src->is_constant(), "should not call otherwise");
724 LIR_Const* c = src->as_constant_ptr();
758 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
759 assert(src->is_constant(), "should not call otherwise");
761 LIR_Const* c = src->as_constant_ptr();
843 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
844 assert(src->is_register(), "should not call otherwise");
850 if (src->type() == T_LONG) {
852 move_regs(src->as_register_lo(), dest->as_register());
856 assert(src->is_single_cpu(), "must match");
857 if (src->type() == T_OBJECT) {
858 __ verify_oop(src->as_register());
860 move_regs(src->as_register(), dest->as_register());
864 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
866 __ verify_oop(src->as_register());
867 move_regs(src->as_register(), dest->as_register_lo());
871 assert(src->is_double_cpu(), "must match");
872 Register f_lo = src->as_register_lo();
873 Register f_hi = src->as_register_hi();
899 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
900 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
902 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
903 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
905 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
908 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
914 assert(src->is_single_xmm(), "must match");
915 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
917 assert(src->is_double_xmm(), "must match");
918 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
922 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
923 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
929 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
930 assert(src->is_register(), "should not call otherwise");
933 if (src->is_single_cpu()) {
936 __ verify_oop(src->as_register());
937 __ movptr (dst, src->as_register());
939 __ movl (dst, src->as_register());
942 } else if (src->is_double_cpu()) {
945 __ movptr (dstLO, src->as_register_lo());
946 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
948 } else if (src->is_single_xmm()) {
950 __ movflt(dst_addr, src->as_xmm_float_reg());
952 } else if (src->is_double_xmm()) {
954 __ movdbl(dst_addr, src->as_xmm_double_reg());
956 } else if (src->is_single_fpu()) {
957 assert(src->fpu_regnr() == 0, "argument must be on TOS");
962 } else if (src->is_double_fpu()) {
963 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
974 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
980 __ verify_oop(src->as_register());
983 __ movptr(compressed_src, src->as_register());
998 if (src->is_single_xmm()) {
999 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1001 assert(src->is_single_fpu(), "must be");
1002 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1010 if (src->is_double_xmm()) {
1011 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1013 assert(src->is_double_fpu(), "must be");
1014 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1026 __ movptr(as_Address(to_addr), src->as_register());
1030 __ movptr(as_Address(to_addr), src->as_register());
1033 __ movl(as_Address(to_addr), src->as_register());
1037 Register from_lo = src->as_register_lo();
1038 Register from_hi = src->as_register_hi();
1073 Register src_reg = src->as_register();
1082 __ movw(as_Address(to_addr), src->as_register());
1098 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1099 assert(src->is_stack(), "should not call otherwise");
1104 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1107 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1111 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1112 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1117 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1121 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1126 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1131 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1140 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1141 if (src->is_single_stack()) {
1143 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1147 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1151 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1156 } else if (src->is_double_stack()) {
1158 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1161 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1162 // push and pop the part at src + wordSize, adding wordSize for the previous push
1163 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1174 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1175 assert(src->is_address(), "should not call otherwise");
1178 LIR_Address* addr = src->as_address_ptr();
1344 void LIR_Assembler::prefetchr(LIR_Opr src) {
1345 LIR_Address* addr = src->as_address_ptr();
1365 void LIR_Assembler::prefetchw(LIR_Opr src) {
1366 LIR_Address* addr = src->as_address_ptr();
1459 LIR_Opr src = op->in_opr();
1465 __ movl2ptr(dest->as_register_lo(), src->as_register());
1467 move_regs(src->as_register(), dest->as_register_lo());
1468 move_regs(src->as_register(), dest->as_register_hi());
1475 __ movl(dest->as_register(), src->as_register_lo());
1477 move_regs(src->as_register_lo(), dest->as_register());
1482 move_regs(src->as_register(), dest->as_register());
1487 move_regs(src->as_register(), dest->as_register());
1492 move_regs(src->as_register(), dest->as_register());
1500 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1502 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1504 assert(src->fpu() == dest->fpu(), "register must be equal");
1512 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1514 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1517 __ movl(Address(rsp, 0), src->as_register());
1524 if (src->is_single_xmm()) {
1525 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1526 } else if (src->is_double_xmm()) {
1527 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1529 assert(src->fpu() == 0, "input must be on TOS");
1548 __ movptr(Address(rsp, 0), src->as_register_lo());
1549 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1556 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1557 assert(src->fpu() == 0, "input must be on TOS");
1935 assert(newval != NULL, "new val must be register");
1972 assert(newval != NULL, "new val must be register");
2467 int val = right->as_constant_ptr()->as_jint();
2469 case lir_logic_and: __ andl (reg, val); break;
2470 case lir_logic_or: __ orl (reg, val); break;
2471 case lir_logic_xor: __ xorl (reg, val); break;
3058 Register src = op->src()->as_register();
3087 store_parameter(src, 4);
3088 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3139 __ push(src);
3168 __ movptr (src, Address(rsp, 4*BytesPerWord));
3208 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3210 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3217 __ testptr(src, src);
3270 // For object arrays, if src is a sub class of dst then we can
3274 __ push(src);
3277 __ load_klass(src, src);
3280 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3282 __ push(src);
3286 __ pop(src);
3288 __ cmpl(src, 0);
3293 __ pop(src);
3297 // src is not a sub class of dst so we have to do a
3306 __ load_klass(tmp, src);
3323 store_parameter(src, 4);
3334 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3341 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3395 __ movptr (src, Address(rsp, 4*BytesPerWord));
3407 __ pop(src);
3414 // primitive case the types must match exactly with src.klass and
3417 // dst type is exactly the expected type and the src type is a
3418 // subtype which we can't check or src is the same array as dst
3440 __ cmpptr(src, dst);
3457 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3463 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3665 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3672 if (src->is_double_xmm()) {
3675 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3677 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3678 __ psrlq(src->as_xmm_double_reg(), 32);
3679 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3682 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3684 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3690 if (src->is_double_stack()) {
3691 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3692 } else if (src->is_address()) {
3693 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3698 } else if (src->is_double_fpu()) {
3699 assert(src->fpu_regnrLo() == 0, "must be TOS");
3710 if (src->is_double_stack()) {
3711 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3712 } else if (src->is_address()) {
3713 __ fild_d(as_Address(src->as_address_ptr()));
3772 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3780 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3782 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3790 __ xchgl(obj, as_Address(src->as_address_ptr()));
3793 __ xchgptr(obj, as_Address(src->as_address_ptr()));
3796 __ xchgl(obj, as_Address(src->as_address_ptr()));
3805 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
3807 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));