Lines Matching defs:lreg
2051 Register lreg = left->as_register();
2057 case lir_add: __ addl (lreg, rreg); break;
2058 case lir_sub: __ subl (lreg, rreg); break;
2059 case lir_mul: __ imull(lreg, rreg); break;
2067 case lir_add: __ addl(lreg, raddr); break;
2068 case lir_sub: __ subl(lreg, raddr); break;
2077 __ incrementl(lreg, c);
2081 __ decrementl(lreg, c);
2165 XMMRegister lreg = left->as_xmm_float_reg();
2170 case lir_add: __ addss(lreg, rreg); break;
2171 case lir_sub: __ subss(lreg, rreg); break;
2173 case lir_mul: __ mulss(lreg, rreg); break;
2175 case lir_div: __ divss(lreg, rreg); break;
2189 case lir_add: __ addss(lreg, raddr); break;
2190 case lir_sub: __ subss(lreg, raddr); break;
2192 case lir_mul: __ mulss(lreg, raddr); break;
2194 case lir_div: __ divss(lreg, raddr); break;
2202 XMMRegister lreg = left->as_xmm_double_reg();
2206 case lir_add: __ addsd(lreg, rreg); break;
2207 case lir_sub: __ subsd(lreg, rreg); break;
2209 case lir_mul: __ mulsd(lreg, rreg); break;
2211 case lir_div: __ divsd(lreg, rreg); break;
2225 case lir_add: __ addsd(lreg, raddr); break;
2226 case lir_sub: __ subsd(lreg, raddr); break;
2228 case lir_mul: __ mulsd(lreg, raddr); break;
2230 case lir_div: __ divsd(lreg, raddr); break;
2590 Register lreg = left->as_register();
2597 assert(lreg == rax, "must be rax,");
2601 __ subl(lreg, rdx);
2604 __ addl(lreg, rdx);
2606 __ sarl(lreg, log2_intptr(divisor));
2607 move_regs(lreg, dreg);
2610 __ mov(dreg, lreg);
2622 assert(lreg == rax, "left register must be rax,");
2626 move_regs(lreg, rax);