Lines Matching defs:dest
634 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
636 assert(dest->is_register(), "should not call otherwise");
642 __ movl(dest->as_register(), c->as_jint());
648 __ movptr(dest->as_register(), c->as_jint());
655 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
657 __ movptr(dest->as_register_lo(), c->as_jint_lo());
658 __ movptr(dest->as_register_hi(), c->as_jint_hi());
665 jobject2reg_with_patching(dest->as_register(), info);
667 __ movoop(dest->as_register(), c->as_jobject());
673 if (dest->is_single_xmm()) {
675 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
677 __ movflt(dest->as_xmm_float_reg(),
681 assert(dest->is_single_fpu(), "must be");
682 assert(dest->fpu_regnr() == 0, "dest must be TOS");
695 if (dest->is_double_xmm()) {
697 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
699 __ movdbl(dest->as_xmm_double_reg(),
703 assert(dest->is_double_fpu(), "must be");
704 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
721 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
723 assert(dest->is_stack(), "should not call otherwise");
729 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
733 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
737 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
743 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
746 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
748 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
758 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
760 assert(dest->is_address(), "should not call otherwise");
762 LIR_Address* addr = dest->as_address_ptr();
843 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
845 assert(dest->is_register(), "should not call otherwise");
848 if (dest->is_single_cpu()) {
852 move_regs(src->as_register_lo(), dest->as_register());
860 move_regs(src->as_register(), dest->as_register());
862 } else if (dest->is_double_cpu()) {
867 move_regs(src->as_register(), dest->as_register_lo());
874 Register t_lo = dest->as_register_lo();
875 Register t_hi = dest->as_register_hi();
899 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
902 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
905 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
907 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
908 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
910 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
913 } else if (dest->is_single_xmm()) {
915 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
916 } else if (dest->is_double_xmm()) {
918 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
921 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
923 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
929 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
931 assert(dest->is_stack(), "should not call otherwise");
934 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
943 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
944 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
949 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
953 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
958 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
964 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
974 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
975 LIR_Address* to_addr = dest->as_address_ptr();
1098 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1100 assert(dest->is_register(), "should not call otherwise");
1102 if (dest->is_single_cpu()) {
1104 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1105 __ verify_oop(dest->as_register());
1107 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1110 } else if (dest->is_double_cpu()) {
1113 __ movptr(dest->as_register_lo(), src_addr_LO);
1114 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1116 } else if (dest->is_single_xmm()) {
1118 __ movflt(dest->as_xmm_float_reg(), src_addr);
1120 } else if (dest->is_double_xmm()) {
1122 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1124 } else if (dest->is_single_fpu()) {
1125 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1129 } else if (dest->is_double_fpu()) {
1130 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1140 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1144 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1148 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1152 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1159 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1164 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1165 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1174 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1176 assert(dest->is_register(), "should not call otherwise");
1186 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1191 __ xorptr(dest->as_register(), dest->as_register());
1207 if (dest->is_single_xmm()) {
1208 __ movflt(dest->as_xmm_float_reg(), from_addr);
1210 assert(dest->is_single_fpu(), "must be");
1211 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1218 if (dest->is_double_xmm()) {
1219 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1221 assert(dest->is_double_fpu(), "must be");
1222 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1231 __ movl(dest->as_register(), from_addr);
1233 __ movptr(dest->as_register(), from_addr);
1238 __ movptr(dest->as_register(), from_addr);
1241 __ movl(dest->as_register(), from_addr);
1245 Register to_lo = dest->as_register_lo();
1246 Register to_hi = dest->as_register_hi();
1290 Register dest_reg = dest->as_register();
1303 Register dest_reg = dest->as_register();
1314 Register dest_reg = dest->as_register();
1336 __ decode_heap_oop(dest->as_register());
1339 __ verify_oop(dest->as_register());
1460 LIR_Opr dest = op->result_opr();
1465 __ movl2ptr(dest->as_register_lo(), src->as_register());
1467 move_regs(src->as_register(), dest->as_register_lo());
1468 move_regs(src->as_register(), dest->as_register_hi());
1469 __ sarl(dest->as_register_hi(), 31);
1475 __ movl(dest->as_register(), src->as_register_lo());
1477 move_regs(src->as_register_lo(), dest->as_register());
1482 move_regs(src->as_register(), dest->as_register());
1483 __ sign_extend_byte(dest->as_register());
1487 move_regs(src->as_register(), dest->as_register());
1488 __ andl(dest->as_register(), 0xFFFF);
1492 move_regs(src->as_register(), dest->as_register());
1493 __ sign_extend_short(dest->as_register());
1499 if (dest->is_single_xmm()) {
1500 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1501 } else if (dest->is_double_xmm()) {
1502 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1504 assert(src->fpu() == dest->fpu(), "register must be equal");
1511 if (dest->is_single_xmm()) {
1512 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1513 } else if (dest->is_double_xmm()) {
1514 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1516 assert(dest->fpu() == 0, "result must be on TOS");
1525 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1527 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1532 __ movl(dest->as_register(), Address(rsp, 0));
1538 __ cmpl(dest->as_register(), 0x80000000);
1545 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1546 assert(dest->fpu() == 0, "result must be on TOS");
1558 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
2046 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2050 assert(left == dest, "left and dest must be equal");
2092 assert(left == dest, "left and dest must be equal");
2164 assert(left == dest, "left and dest must be equal");
2200 assert(left == dest, "left and dest must be equal");
2236 assert(dest->is_single_fpu(), "fpu stack allocation required");
2239 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2243 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2269 assert(dest->is_double_fpu(), "fpu stack allocation required");
2278 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2282 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2308 __ fmulp(dest->fpu_regnrLo() + 1);
2312 assert(left == dest, "left and dest must be equal");
2411 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2416 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2417 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2419 __ andpd(dest->as_xmm_double_reg(),
2424 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2430 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2817 Register dest = dst->as_register();
2819 __ movl(dest, -1);
2821 __ set_byte_if_not_zero(dest);
2822 __ movzbl(dest, dest);
2948 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2952 // * left and dest must be equal
2955 assert(left == dest, "left and dest must be equal");
2994 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2995 if (dest->is_single_cpu()) {
2996 // first move left into dest so that left is not destroyed by the shift
2997 Register value = dest->as_register();
3007 } else if (dest->is_double_cpu()) {
3011 // first move left into dest so that left is not destroyed by the shift
3012 Register value = dest->as_register_lo();
3598 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3601 move_regs(left->as_register(), dest->as_register());
3606 Register dst = dest->as_register_lo();
3612 if (dest->as_register_lo() == hi) {
3613 assert(dest->as_register_hi() != lo, "destroying register");
3614 move_regs(hi, dest->as_register_hi());
3615 move_regs(lo, dest->as_register_lo());
3617 move_regs(lo, dest->as_register_lo());
3618 move_regs(hi, dest->as_register_hi());
3622 } else if (dest->is_single_xmm()) {
3623 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3624 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3626 __ xorps(dest->as_xmm_float_reg(),
3629 } else if (dest->is_double_xmm()) {
3630 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3631 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3633 __ xorpd(dest->as_xmm_double_reg(),
3638 assert(dest->fpu() == 0, "dest must be TOS");
3647 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3648 assert(addr->is_address() && dest->is_register(), "check");
3650 reg = dest->as_pointer_register();
3656 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3658 __ call(RuntimeAddress(dest));
3665 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3673 if (dest->is_double_cpu()) {
3675 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3677 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3679 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3681 } else if (dest->is_double_stack()) {
3682 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3683 } else if (dest->is_address()) {
3684 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3689 } else if (dest->is_double_xmm()) {
3691 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3693 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3700 if (dest->is_double_stack()) {
3701 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3702 } else if (dest->is_address()) {
3703 __ fistp_d(as_Address(dest->as_address_ptr()));
3708 } else if (dest->is_double_fpu()) {
3709 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3772 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3773 assert(data == dest, "xchg/xadd uses only 2 operands");