Cross Reference: /openjdk7/hotspot/src/cpu/x86/vm/assembler

Lines Matching defs:pre
580                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
582                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
585                   int nds_enc, VexSimdPrefix pre, VexOpcode opc,
589                   VexSimdPrefix pre, VexOpcode opc,
593                   VexSimdPrefix pre, bool vector256 = false) {
596     vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256);
600                              VexSimdPrefix pre, VexOpcode opc,
604                              VexSimdPrefix pre, bool vector256 = false,
609     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256);
613                    VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
617                    VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
618     simd_prefix(dst, xnoreg, src, pre, opc);
621   void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
622     simd_prefix(src, dst, pre);
625                      VexSimdPrefix pre) {
627     simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
631                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
636                              VexSimdPrefix pre) {
640     return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre);
642   int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) {
643     return simd_prefix_and_encode(dst, xnoreg, src, pre);
646                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
647     return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc);
652                                VexSimdPrefix pre) {
654     return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w);
656   int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) {
657     return simd_prefix_and_encode_q(dst, xnoreg, src, pre);
660                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
662     return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w);
675   void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
676   void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
677   void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
678   void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
680                       Address src, VexSimdPrefix pre, bool vector256);
682                       XMMRegister src, VexSimdPrefix pre, bool vector256);