Lines Matching refs:vector256
1716 bool vector256 = true;
1717 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1725 bool vector256 = true;
1726 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1734 bool vector256 = true;
1737 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
2481 bool vector256 = true;
2485 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
2492 bool vector256 = true;
2493 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
2896 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2901 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2906 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2911 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2916 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2921 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2926 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2931 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2936 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2941 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2946 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2951 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2956 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2961 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2966 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2971 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2988 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2990 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
2993 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2995 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
2998 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3000 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3003 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3005 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3018 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3020 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3023 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3025 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3028 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3030 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3033 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3035 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3048 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3050 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3053 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3055 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3058 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3060 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3063 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3065 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3078 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3080 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3083 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3085 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3088 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3090 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3093 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3095 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3118 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3120 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3123 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3125 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3128 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3130 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3133 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3135 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3158 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3160 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3163 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3165 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3168 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3170 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3173 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3175 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3200 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3201 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3202 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3205 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3206 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3207 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3210 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3211 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3212 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3215 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3216 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3217 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3220 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3221 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3222 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3225 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3226 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3227 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3230 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3231 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3232 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3235 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3236 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3237 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3260 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3261 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3262 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3265 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3266 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3267 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3270 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3271 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3272 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3275 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3276 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3277 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3280 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3281 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3282 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3285 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3286 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3287 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3290 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3291 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3292 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3295 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3296 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3297 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3312 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3313 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3314 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3317 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3318 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3319 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3324 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3325 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3326 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3329 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3330 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3334 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3382 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3383 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3385 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3389 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3390 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3392 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3396 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3397 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3399 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3403 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3404 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3405 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3408 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3409 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3410 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3413 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3414 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3415 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3463 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3464 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3466 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3470 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3471 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3473 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3477 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3478 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3480 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3484 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3485 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3486 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3489 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3490 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3491 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3494 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3495 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3496 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3528 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3529 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3531 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3535 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3536 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3538 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3542 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3543 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3544 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3547 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3548 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3549 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3559 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3560 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3561 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3564 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3565 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3566 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3574 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3575 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3576 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3579 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3580 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3581 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3589 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3590 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3591 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3594 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3595 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3596 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3602 bool vector256 = true;
3603 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3614 bool vector256 = true;
3618 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3628 bool vector256 = true;
3631 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3640 bool vector256 = true;
3641 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3652 bool vector256 = true;
3656 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3666 bool vector256 = true;
3669 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3679 bool vector256 = true;
3680 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
4205 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
4215 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
4223 byte1 |= (vector256 ? 4 : 0) | pre;
4228 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
4232 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4235 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
4239 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4244 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4248 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4255 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4260 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4296 Address src, VexSimdPrefix pre, bool vector256) {
4298 vex_prefix(dst, nds, src, pre, vector256);
4304 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4305 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
8494 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
8496 vandpd(dst, nds, as_Address(src), vector256);
8499 vandpd(dst, nds, Address(rscratch1, 0), vector256);
8503 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
8505 vandps(dst, nds, as_Address(src), vector256);
8508 vandps(dst, nds, Address(rscratch1, 0), vector256);
8566 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
8568 vxorpd(dst, nds, as_Address(src), vector256);
8571 vxorpd(dst, nds, Address(rscratch1, 0), vector256);
8575 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
8577 vxorps(dst, nds, as_Address(src), vector256);
8580 vxorps(dst, nds, Address(rscratch1, 0), vector256);