Lines Matching refs:opcode
224 assert(isByte(op1) && isByte(op2), "wrong opcode");
234 assert(isByte(op1) && isByte(op2), "wrong opcode");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
275 assert(isByte(op1) && isByte(op2), "wrong opcode");
286 assert(isByte(op1) && isByte(op2), "wrong opcode");
560 ip++; // skip opcode
690 ip++; // opcode
701 ip++; // skip opcode
893 assert(isByte(b1) && isByte(b2), "wrong opcode");
4166 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
4169 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
4267 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4270 emit_byte(opcode);
4274 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4276 emit_byte(opcode);
4281 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4284 emit_byte(opcode);
4288 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4290 emit_byte(opcode);
4295 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4299 emit_byte(opcode);
4303 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4306 emit_byte(opcode);
4435 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal