Lines Matching refs:r_1

505                         VMReg r_1, Register base, const int st_off);
631 VMReg r_1, Register base, const int st_off) {
635 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
638 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
698 VMReg r_1 = regs[i].first();
700 if (!r_1->is_valid()) {
704 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
705 RegisterOrConstant ld_off = reg2offset(r_1) + extraspace + bias;
707 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
712 if (r_1->is_Register()) {
713 Register r = r_1->as_Register()->after_restore();
722 assert(r_1->is_FloatRegister(), "");
724 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
727 store_c2i_double(r_2, r_1, base, st_off);
934 VMReg r_1 = regs[i].first();
936 if (!r_1->is_valid()) {
940 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
941 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
942 if (r_2->is_valid()) r_2 = r_1->next();
944 if (r_1->is_Register()) { // Register argument
945 Register r = r_1->as_Register()->after_restore();
960 assert(r_1->is_FloatRegister(), "");
962 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
971 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
974 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
982 assert(r_1->as_FloatRegister() == F8, "fix this code");
987 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
988 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);