57   bool is_call()                       { return is_op(long_at(0), Assembler::call_op); }
58   bool is_sethi()                      { return (is_op2(long_at(0), Assembler::sethi_op2)
66     return (is_op(x, Assembler::arith_op) &&
67             (inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3);
74                     Assembler::ldsw_op3 : Assembler::lduw_op3,
75                   Assembler::ldst_op)
76         && Assembler::inv_rs1(x) == G0
77         && Assembler::inv_rd(x) == O7;
84     return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op)
92     return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2);
97     return is_op2(x, Assembler::fbp_op2) || is_op2(x, Assembler::fb_op2);
104     return (is_int_jump() && Assembler::inv_cond(x) != Assembler::always) ||
105            (is_float_jump() && Assembler::inv_cond(x) != Assembler::f_always);
110     return is_op3(x, Assembler::stw_op3, Assembler::ldst_op) &&
116     return is_op3(x, Assembler::prefetch_op3, Assembler::ldst_op);
121     return is_op3(x, Assembler::membar_op3, Assembler::arith_op) &&
128     return is_op3(x, Assembler::ldx_op3,  Assembler::ldst_op) &&
130     return is_op3(x, Assembler::lduw_op3, Assembler::ldst_op) &&
132       (inv_rd(x) == G0) && (inv_immed(x) ? Assembler::inv_simm13(x) == 0 : inv_rs2(x) == G0);
140   static int rdpc_instruction()        { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | Assembler::u_field(5, 18, 14) | Assembler::rd(O7); }
142   // Temporary fix: in optimized mode, u_field is a macro for efficiency reasons (see Assembler::u_field) - needs to be fixed
143   static int rdpc_instruction()        { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) |            u_field(5, 18, 14) | Assembler::rd(O7); }
145   static int nop_instruction()         { return Assembler::op(Assembler::branch_op) | Assembler::op2(Assembler::sethi_op2); }
147   static int call_instruction(address destination, address pc) { return Assembler::op(Assembler::call_op) | Assembler::wdisp((intptr_t)destination, (intptr_t)pc, 30); }
149   static int branch_instruction(Assembler::op2s op2val, Assembler::Condition c, bool a) {
150     return Assembler::op(Assembler::branch_op) | Assembler::op2(op2val) | Assembler::annul(a) | Assembler::cond(c);
153   static int op3_instruction(Assembler::ops opval, Register rd, Assembler::op3s op3val, Register rs1, int simm13a) {
154     return Assembler::op(opval) | Assembler::rd(rd) | Assembler::op3(op3val) | Assembler::rs1(rs1) | Assembler::immed(true) | Assembler::simm(simm13a, 13);
158     return Assembler::op(Assembler::branch_op) | Assembler::rd(rd) | Assembler::op2(Assembler::sethi_op2) | Assembler::hi22(imm22a);
171   static bool is_op( int x, Assembler::ops opval)  {
172     return Assembler::inv_op(x) == opval;
174   static bool is_op2(int x, Assembler::op2s op2val) {
175     return Assembler::inv_op(x) == Assembler::branch_op && Assembler::inv_op2(x) == op2val;
177   static bool is_op3(int x, Assembler::op3s op3val, Assembler::ops opval) {
178     return Assembler::inv_op(x) == opval && Assembler::inv_op3(x) == op3val;
182   static Register inv_rd(  int x ) { return Assembler::inv_rd( x); }
183   static Register inv_rs1( int x ) { return Assembler::inv_rs1(x); }
184   static Register inv_rs2( int x ) { return Assembler::inv_rs2(x); }
186   static bool inv_immed( int x ) { return Assembler::inv_immed(x); }
187   static bool inv_annul( int x ) { return (Assembler::annul(true) & x) != 0; }
188   static int  inv_cond(  int x ) { return Assembler::inv_cond(x); }
190   static int inv_op(  int x ) { return Assembler::inv_op( x); }
191   static int inv_op2( int x ) { return Assembler::inv_op2(x); }
192   static int inv_op3( int x ) { return Assembler::inv_op3(x); }
194   static int inv_simm(    int x, int nbits ) { return Assembler::inv_simm(x, nbits); }
195   static intptr_t inv_wdisp(   int x, int nbits ) { return Assembler::inv_wdisp(  x, 0, nbits); }
196   static intptr_t inv_wdisp16( int x )            { return Assembler::inv_wdisp16(x, 0); }
197   static int branch_destination_offset(int x) { return Assembler::branch_destination(x, 0); }
199     return Assembler::patched_branch(dest_offset, x, 0);
201   void set_annul_bit() { set_long_at(0, long_at(0) | Assembler::annul(true)); }
211     // cf. Assembler::assert_signed_range()
218     return (insn &~ Assembler::simm(-1, nbits)) | Assembler::simm(imm, nbits);
223     return (insn &~ Assembler::wdisp((intptr_t)-4, (intptr_t)0, nbits)) | Assembler::wdisp(disp, 0, nbits);
227     return (insn &~ Assembler::wdisp16((intptr_t)-4, 0)) | Assembler::wdisp16(disp, 0);
232     assert(is_either(Assembler::inv_op(insn),
233                      Assembler::arith_op, Assembler::ldst_op) &&
234             (insn & Assembler::immed(true)), "must have a simm13 field");
235     return Assembler::inv_simm(insn, 13);
246     assert(is_op2(*(unsigned int *)pc, Assembler::sethi_op2), "must be sethi");
261     assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi");
262     int hi = Assembler::inv_hi22(sethi_insn);
269     // note that Assembler::hi22 clips the low 10 bits for us
270     assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi");
271     return (sethi_insn &~ Assembler::hi22(-1)) | Assembler::hi22(imm);
276     int imm10 = Assembler::low10(imm);
277     return (arith_insn &~ Assembler::simm(-1, 13)) | Assembler::simm(imm10, 13);
281     return Assembler::low10(imm);
292     assert(is_op2(*pc, Assembler::sethi_op2), "in gethi - must be sethi");
293     adr = (unsigned int)Assembler::inv_hi22( *(pc++) );
298        assert ( Assembler::inv_op(*pc) == Assembler::arith_op, "in gethi - must be arith_op" );
299        switch  ( Assembler::inv_op3(*pc) ) {
300          case Assembler::xor_op3:
304          case Assembler::sll_op3:
307          case Assembler::or_op3:
638     op3_mask_ld = 1 << Assembler::lduw_op3 |
639                   1 << Assembler::ldub_op3 |
640                   1 << Assembler::lduh_op3 |
641                   1 << Assembler::ldd_op3 |
642                   1 << Assembler::ldsw_op3 |
643                   1 << Assembler::ldsb_op3 |
644                   1 << Assembler::ldsh_op3 |
645                   1 << Assembler::ldx_op3,
646     op3_mask_st = 1 << Assembler::stw_op3 |
647                   1 << Assembler::stb_op3 |
648                   1 << Assembler::sth_op3 |
649                   1 << Assembler::std_op3 |
650                   1 << Assembler::stx_op3,
651     op3_ldst_int_limit = Assembler::ldf_op3,
652     op3_mask_ldf = 1 << (Assembler::ldf_op3  - op3_ldst_int_limit) |
653                    1 << (Assembler::lddf_op3 - op3_ldst_int_limit),
654     op3_mask_stf = 1 << (Assembler::stf_op3  - op3_ldst_int_limit) |
655                    1 << (Assembler::stdf_op3 - op3_ldst_int_limit),
669     return (is_op(i0, Assembler::ldst_op));
730     op3_mask_ld = 1 << Assembler::lduw_op3 |
731                   1 << Assembler::ldub_op3 |
732                   1 << Assembler::lduh_op3 |
733                   1 << Assembler::ldd_op3 |
734                   1 << Assembler::ldsw_op3 |
735                   1 << Assembler::ldsb_op3 |
736                   1 << Assembler::ldsh_op3 |
737                   1 << Assembler::ldx_op3,
738     op3_mask_st = 1 << Assembler::stw_op3 |
739                   1 << Assembler::stb_op3 |
740                   1 << Assembler::sth_op3 |
741                   1 << Assembler::std_op3 |
742                   1 << Assembler::stx_op3,
743     op3_ldst_int_limit = Assembler::ldf_op3,
744     op3_mask_ldf = 1 << (Assembler::ldf_op3  - op3_ldst_int_limit) |
745                    1 << (Assembler::lddf_op3 - op3_ldst_int_limit),
746     op3_mask_stf = 1 << (Assembler::stf_op3  - op3_ldst_int_limit) |
747                    1 << (Assembler::stdf_op3 - op3_ldst_int_limit),
762     return (is_op(i0, Assembler::ldst_op));
895   Assembler::Condition condition() {
897     return (Assembler::Condition) Assembler::inv_cond(x);

Indexes created Tue Jul 24 14:28:13 CEST 2018