Lines Matching refs:to_reg
908 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
915 load_offset = load(base, O7, to_reg, type, wide);
920 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
921 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
922 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
923 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
927 __ ldx(base, offset, to_reg->as_register_lo());
929 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
931 __ ldd(base, offset, to_reg->as_register_hi());
935 assert(base != to_reg->as_register_lo(), "can't handle this");
936 assert(O7 != to_reg->as_register_lo(), "can't handle this");
937 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
939 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
940 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
942 if (base == to_reg->as_register_lo()) {
943 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
944 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
946 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
947 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
952 case T_ADDRESS: __ ld_ptr(base, offset, to_reg->as_register()); break;
957 __ lduw(base, offset, to_reg->as_register());
958 __ decode_heap_oop(to_reg->as_register());
960 __ ld_ptr(base, offset, to_reg->as_register());
964 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
967 FloatRegister reg = to_reg->as_double_reg();
973 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
980 __ verify_oop(to_reg->as_register());
987 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
991 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
992 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
993 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
994 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
995 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
1000 __ lduw(base, disp, to_reg->as_register());
1001 __ decode_heap_oop(to_reg->as_register());
1003 __ ld_ptr(base, disp, to_reg->as_register());
1007 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1008 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1011 __ ldx(base, disp, to_reg->as_register_lo());
1013 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1015 __ ldd(base, disp, to_reg->as_register_hi());
1021 __ verify_oop(to_reg->as_register());
1169 LIR_Opr to_reg = dest;
1176 if (to_reg->is_single_cpu()) {
1178 __ set(con, to_reg->as_register());
1181 assert(to_reg->is_single_fpu(), "wrong register kind");
1186 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1195 if (to_reg->is_double_cpu()) {
1197 __ set(con, to_reg->as_register_lo());
1199 __ set(low(con), to_reg->as_register_lo());
1200 __ set(high(con), to_reg->as_register_hi());
1203 } else if (to_reg->is_single_cpu()) {
1204 __ set(con, to_reg->as_register());
1208 assert(to_reg->is_double_fpu(), "wrong register kind");
1215 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1223 jobject2reg(c->as_jobject(), to_reg->as_register());
1225 jobject2reg_with_patching(to_reg->as_register(), info);
1239 if (to_reg->is_single_fpu()) {
1242 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1245 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1248 __ ld(O7, 0, to_reg->as_register());
1262 if (to_reg->is_double_fpu()) {
1266 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1268 assert(to_reg->is_double_cpu(), "Must be a long register.");
1270 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1272 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1273 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1350 LIR_Opr to_reg = dest;
1364 assert(!to_reg->is_double_cpu() ||
1393 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1396 offset = load(src, disp_reg, to_reg, type, wide);
1451 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1452 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1455 assert(to_reg->is_double_fpu(), "should match");
1456 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1459 assert(to_reg->is_single_fpu(), "should match");
1460 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1462 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1465 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1467 assert(to_reg->is_double_cpu() &&
1468 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1469 from_reg->as_register_lo() != to_reg->as_register_hi(),
1472 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1473 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1476 } else if (to_reg->is_double_cpu()) {
1478 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1482 __ mov(from_reg->as_register(), to_reg->as_register());
1487 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1488 __ verify_oop(to_reg->as_register());