Cross Reference: /openjdk7/hotspot/src/cpu/sparc/vm/c1_LIRAssembler

Lines Matching +defs:val +defs:src
79       LIR_Opr src = op1->in_opr();
82       if (src == dst) {
84         // this works around a problem where moves with the same src and dst
98       if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
99           ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
105         if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
109         if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
111         } else if (src->is_single_stack()) {
116       if (src->is_register()) {
125           ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
126            (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
727       LIR_Opr val = op->in_opr();
728       FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
1026 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1027   LIR_Const* c = src->as_constant_ptr();
1088 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
1089   LIR_Const* c = src->as_constant_ptr();
1167 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1168   LIR_Const* c = src->as_constant_ptr();
1297 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1302       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1310       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1319       Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1352   Register src = addr->base()->as_pointer_register();
1358     __ verify_oop(src);
1379     __ add(src, addr->index()->as_register(), O7);
1380     src = O7;
1393     offset = load(src, disp_value, to_reg, type, wide, unaligned);
1396     offset = load(src, disp_reg, to_reg, type, wide);
1400     patching_epilog(patch, patch_code, src, info);
1406 void LIR_Assembler::prefetchr(LIR_Opr src) {
1407   LIR_Address* addr = src->as_address_ptr();
1416 void LIR_Assembler::prefetchw(LIR_Opr src) {
1417   LIR_Address* addr = src->as_address_ptr();
1426 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1428   if (src->is_single_word()) {
1429     addr = frame_map()->address_for_slot(src->single_stack_ix());
1430   } else if (src->is_double_word())  {
1431     addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1498   Register src = addr->base()->as_pointer_register();
1504     __ verify_oop(src);
1525     __ add(src, addr->index()->as_register(), O7);
1526     src = O7;
1539     offset = store(from_reg, src, disp_value, type, wide, unaligned);
1542     offset = store(from_reg, src, disp_reg, type, wide);
1546     patching_epilog(patch, patch_code, src, info);
2062   Register src = op->src()->as_register();
2090     __ mov(src,     O0);
2125   // make sure src and dst are non-null and load array length
2127     __ tst(src);
2157     __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2180         __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
2185         __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2192       // For object arrays, if src is a sub class of dst then we can
2199       __ load_klass(src, G3);
2209         // src is not a sub class of dst so we have to do a
2222             __ load_klass(src, tmp);
2243         __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2304     // primitive case the types must match exactly with src.klass and
2307     // dst type is exactly the expected type and the src type is a
2308     // subtype which we can't check or src is the same array as dst
2322         // load the raw value of the src klass.
2323         __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2328         __ delayed()->cmp(src, dst);
2337         __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2342         __ delayed()->cmp(src, dst);
2364   __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
3162 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3169     LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3188     if (src->is_register() && dest->is_address()) {
3192         __ srl (src->as_register_lo(),  0, G5);
3193         __ sllx(src->as_register_hi(), 32, G4);
3203         __ mov (src->as_register_hi(), G4);
3204         __ mov (src->as_register_lo(), G5);
3212     } else if (src->is_address() && dest->is_register()) {
3242     move_op(src, dest, type, lir_patch_none, info, false, false, false);
3281 // src and src->successor() are packed into dst
3282 // src and dst may be the same register.
3283 // Note: src is destroyed
3284 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3285   Register rs = src->as_register();
3294 // src is unpacked into dst and dst->successor()
3295 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3296   Register rs = src->as_register_lo();
3415 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3416   LIR_Address* addr = src->as_address_ptr();