Cross Reference: /openjdk7/hotspot/src/cpu/sparc/vm/c1_LIRAssembler

Lines Matching defs:dest
518   // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
1026 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1038       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1050       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1057       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1063       Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1088 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
1090   LIR_Address* addr     = dest->as_address_ptr();
1167 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1169   LIR_Opr to_reg = dest;
1297 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1303       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1311       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1320       Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
1346 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1350   LIR_Opr to_reg = dest;
1426 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1435   load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1439 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1441   if (dest->is_single_word()) {
1442     addr = frame_map()->address_for_slot(dest->single_stack_ix());
1443   } else if (dest->is_double_word())  {
1444     addr = frame_map()->address_for_slot(dest->double_stack_ix());
1493 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1496   LIR_Address* addr = dest->as_address_ptr();
1737     Register dest = result->as_register();
1741       __ sethi(opr1->as_jint(), dest);
1760     Register dest = result->as_register();
1762       __ delayed()->or3(G0, opr1->as_jint(), dest);
1765       __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1784 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1787   assert(dest->is_register(), "wrong items state");
1790     if (dest->is_float_kind()) {
1798         res  = dest->as_float_reg();
1803         res  = dest->as_double_reg();
1816     } else if (dest->is_double_cpu()) {
1818       Register dst_lo = dest->as_register_lo();
1838       Register dst_lo = dest->as_register_lo();
1839       Register dst_hi = dest->as_register_hi();
1859       Register res  = dest->as_register();
1871     if (dest->is_single_cpu()) {
1873       Register res  = dest->as_register();
1884       Register res  = dest->as_register_lo();
1904 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1910       assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1916       FloatRegister dst_reg = dest->as_double_reg();
1923       FloatRegister dst_reg = dest->as_double_reg();
1935 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1937     if (dest->is_single_cpu()) {
1940         case lir_logic_and:   __ and3 (left->as_register(), simm13, dest->as_register()); break;
1941         case lir_logic_or:    __ or3  (left->as_register(), simm13, dest->as_register()); break;
1942         case lir_logic_xor:   __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1952           __ and3 (left->as_register_hi(), 0,      dest->as_register_hi());
1954           __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1959           __ or3 (left->as_register_hi(), 0,      dest->as_register_hi());
1961           __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1966           __ xor3 (left->as_register_hi(), 0,      dest->as_register_hi());
1968           __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1977     if (dest->is_single_cpu()) {
1979         case lir_logic_and:   __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1980         case lir_logic_or:    __ or3  (left->as_register(), right->as_register(), dest->as_register()); break;
1981         case lir_logic_xor:   __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1992         case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1993         case lir_logic_or:  __ or3  (l, r, dest->as_register_lo()); break;
1994         case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
2000           __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2001           __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2005           __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2006           __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2010           __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2011           __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2393 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2394   if (dest->is_single_cpu()) {
2398         case lir_shl:  __ sllx  (left->as_register(), count->as_register(), dest->as_register()); break;
2399         case lir_shr:  __ srax  (left->as_register(), count->as_register(), dest->as_register()); break;
2400         case lir_ushr: __ srl   (left->as_register(), count->as_register(), dest->as_register()); break;
2406         case lir_shl:  __ sll   (left->as_register(), count->as_register(), dest->as_register()); break;
2407         case lir_shr:  __ sra   (left->as_register(), count->as_register(), dest->as_register()); break;
2408         case lir_ushr: __ srl   (left->as_register(), count->as_register(), dest->as_register()); break;
2414       case lir_shl:  __ sllx  (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2415       case lir_shr:  __ srax  (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2416       case lir_ushr: __ srlx  (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2421       case lir_shl:  __ lshl  (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2422       case lir_shr:  __ lshr  (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2423       case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2431 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2436     Register d = dest->as_register_lo();
2447   if (dest->is_single_cpu()) {
2450       case lir_shl:  __ sll   (left->as_register(), count, dest->as_register()); break;
2451       case lir_shr:  __ sra   (left->as_register(), count, dest->as_register()); break;
2452       case lir_ushr: __ srl   (left->as_register(), count, dest->as_register()); break;
2455   } else if (dest->is_double_cpu()) {
2458       case lir_shl:  __ sllx  (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2459       case lir_shr:  __ srax  (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2460       case lir_ushr: __ srlx  (left->as_pointer_register(), count, dest->as_pointer_register()); break;
3105 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3109     __ neg(left->as_register(), dest->as_register());
3111     __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3113     __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3119     __ sub(G0, Rlow, dest->as_register_lo());
3121     __ subcc(G0, Rlow, dest->as_register_lo());
3122     __ subc (G0, Rhi,  dest->as_register_hi());
3140 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3147   __ call(dest, relocInfo::runtime_call_type);
3162 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3169     LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3188     if (src->is_register() && dest->is_address()) {
3212     } else if (src->is_address() && dest->is_register()) {
3220         __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3221         __ mov (G5, dest->as_register_lo());     // copy low half into lo
3229         __ mov (G4, dest->as_register_hi());
3230         __ mov (G5, dest->as_register_lo());
3242     move_op(src, dest, type, lir_patch_none, info, false, false, false);
3304 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3308   __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3415 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3418   assert(data == dest, "swap uses only 2 operands");