Lines Matching refs:Register
37 // Register aliases for parts of the system:
64 REGISTER_DECLARATION(Register, G2_thread , G2);
65 REGISTER_DECLARATION(Register, G6_heapbase , G6);
69 REGISTER_DECLARATION(Register, G5_method , G5);
70 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
71 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
74 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
77 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
81 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
82 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
83 REGISTER_DECLARATION(Register, G3_scratch , G3);
84 REGISTER_DECLARATION(Register, G4_scratch , G4);
88 REGISTER_DECLARATION(Register, Gtemp , G5);
91 REGISTER_DECLARATION(Register, G5_method_type , G5);
92 REGISTER_DECLARATION(Register, G3_method_handle , G3);
93 REGISTER_DECLARATION(Register, L7_mh_SP_save , L7);
135 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
140 REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer
141 REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch
142 REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only)
143 REGISTER_DECLARATION(Register, L2_scratch , L2);
144 REGISTER_DECLARATION(Register, L3_scratch , L3);
145 REGISTER_DECLARATION(Register, L4_scratch , L4);
146 REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses
147 REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses
148 REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache
149 REGISTER_DECLARATION(Register, O5_savedSP , O5);
150 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
154 REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler
155 REGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler
158 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
159 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
160 REGISTER_DECLARATION(Register, Lmethod , L2);
161 REGISTER_DECLARATION(Register, Llocals , L3);
162 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
164 REGISTER_DECLARATION(Register, Lmonitors , L4);
165 REGISTER_DECLARATION(Register, Lbyte_code , L5);
169 REGISTER_DECLARATION(Register, Llast_SP , L5);
170 REGISTER_DECLARATION(Register, Lscratch , L5);
171 REGISTER_DECLARATION(Register, Lscratch2 , L6);
172 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
174 REGISTER_DECLARATION(Register, O5_savedSP , O5);
175 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
178 REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables
179 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
180 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
221 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
222 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
228 #define Gthread AS_REGISTER(Register, Gthread)
229 #define Gmethod AS_REGISTER(Register, Gmethod)
230 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
231 #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg)
232 #define Gargs AS_REGISTER(Register, Gargs)
233 #define Lthread_cache AS_REGISTER(Register, Lthread_cache)
234 #define Gframe_size AS_REGISTER(Register, Gframe_size)
235 #define Gtemp AS_REGISTER(Register, Gtemp)
238 #define Lstate AS_REGISTER(Register, Lstate)
239 #define Lesp AS_REGISTER(Register, Lesp)
240 #define L1_scratch AS_REGISTER(Register, L1_scratch)
241 #define Lmirror AS_REGISTER(Register, Lmirror)
242 #define L2_scratch AS_REGISTER(Register, L2_scratch)
243 #define L3_scratch AS_REGISTER(Register, L3_scratch)
244 #define L4_scratch AS_REGISTER(Register, L4_scratch)
245 #define Lscratch AS_REGISTER(Register, Lscratch)
246 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
247 #define L7_scratch AS_REGISTER(Register, L7_scratch)
248 #define Ostate AS_REGISTER(Register, Ostate)
250 #define Lesp AS_REGISTER(Register, Lesp)
251 #define Lbcp AS_REGISTER(Register, Lbcp)
252 #define Lmethod AS_REGISTER(Register, Lmethod)
253 #define Llocals AS_REGISTER(Register, Llocals)
254 #define Lmonitors AS_REGISTER(Register, Lmonitors)
255 #define Lbyte_code AS_REGISTER(Register, Lbyte_code)
256 #define Lscratch AS_REGISTER(Register, Lscratch)
257 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
258 #define LcpoolCache AS_REGISTER(Register, LcpoolCache)
261 #define Lentry_args AS_REGISTER(Register, Lentry_args)
262 #define I5_savedSP AS_REGISTER(Register, I5_savedSP)
263 #define O5_savedSP AS_REGISTER(Register, O5_savedSP)
264 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
265 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
266 #define IdispatchTables AS_REGISTER(Register, IdispatchTables)
268 #define Oexception AS_REGISTER(Register, Oexception)
269 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
276 // Note: A register location is represented via a Register, not
281 Register _base; // Base register.
288 Address(Register base, RegisterOrConstant index_or_disp)
293 Address(Register base, Register index)
298 Address(Register base, int disp)
305 Address(Register base, ByteSize disp)
312 Register base() const { return _base; }
313 Register index() const { return _index_or_disp.as_register(); }
319 bool uses(Register reg) const { return base() == reg || (has_index() && index() == reg); }
541 Register as_register() const {
960 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
961 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
962 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
965 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
968 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
969 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
1232 inline void add(Register s1, Register s2, Register d );
1233 inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1234 inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1235 inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1236 inline void add(const Address& a, Register d, int offset = 0);
1238 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1239 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1240 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
1241 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1242 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1243 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1248 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
1249 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
1252 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
1253 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
1296 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1297 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1301 void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
1302 void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1303 void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
1304 void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1305 void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1306 void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1307 void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1308 void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1369 inline void flush( Register s1, Register s2 );
1370 inline void flush( Register s1, int simm13a);
1393 void jmpl( Register s1, Register s2, Register d );
1394 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1398 inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
1399 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
1400 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
1405 inline void ldfsr( Register s1, Register s2 );
1406 inline void ldfsr( Register s1, int simm13a);
1407 inline void ldxfsr( Register s1, Register s2 );
1408 inline void ldxfsr( Register s1, int simm13a);
1412 inline void ldc( Register s1, Register s2, int crd );
1413 inline void ldc( Register s1, int simm13a, int crd);
1414 inline void lddc( Register s1, Register s2, int crd );
1415 inline void lddc( Register s1, int simm13a, int crd);
1416 inline void ldcsr( Register s1, Register s2, int crd );
1417 inline void ldcsr( Register s1, int simm13a, int crd);
1422 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1423 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1427 inline void ldsb( Register s1, Register s2, Register d );
1428 inline void ldsb( Register s1, int simm13a, Register d);
1429 inline void ldsh( Register s1, Register s2, Register d );
1430 inline void ldsh( Register s1, int simm13a, Register d);
1431 inline void ldsw( Register s1, Register s2, Register d );
1432 inline void ldsw( Register s1, int simm13a, Register d);
1433 inline void ldub( Register s1, Register s2, Register d );
1434 inline void ldub( Register s1, int simm13a, Register d);
1435 inline void lduh( Register s1, Register s2, Register d );
1436 inline void lduh( Register s1, int simm13a, Register d);
1437 inline void lduw( Register s1, Register s2, Register d );
1438 inline void lduw( Register s1, int simm13a, Register d);
1439 inline void ldx( Register s1, Register s2, Register d );
1440 inline void ldx( Register s1, int simm13a, Register d);
1441 inline void ld( Register s1, Register s2, Register d );
1442 inline void ld( Register s1, int simm13a, Register d);
1443 inline void ldd( Register s1, Register s2, Register d );
1444 inline void ldd( Register s1, int simm13a, Register d);
1448 inline void ld( Register s1, ByteSize simm13a, Register d);
1451 inline void ldsb(const Address& a, Register d, int offset = 0);
1452 inline void ldsh(const Address& a, Register d, int offset = 0);
1453 inline void ldsw(const Address& a, Register d, int offset = 0);
1454 inline void ldub(const Address& a, Register d, int offset = 0);
1455 inline void lduh(const Address& a, Register d, int offset = 0);
1456 inline void lduw(const Address& a, Register d, int offset = 0);
1457 inline void ldx( const Address& a, Register d, int offset = 0);
1458 inline void ld( const Address& a, Register d, int offset = 0);
1459 inline void ldd( const Address& a, Register d, int offset = 0);
1461 inline void ldub( Register s1, RegisterOrConstant s2, Register d );
1462 inline void ldsb( Register s1, RegisterOrConstant s2, Register d );
1463 inline void lduh( Register s1, RegisterOrConstant s2, Register d );
1464 inline void ldsh( Register s1, RegisterOrConstant s2, Register d );
1465 inline void lduw( Register s1, RegisterOrConstant s2, Register d );
1466 inline void ldsw( Register s1, RegisterOrConstant s2, Register d );
1467 inline void ldx( Register s1, RegisterOrConstant s2, Register d );
1468 inline void ld( Register s1, RegisterOrConstant s2, Register d );
1469 inline void ldd( Register s1, RegisterOrConstant s2, Register d );
1473 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1474 void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1475 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1476 void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1477 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1478 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1479 void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1480 void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1481 void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1482 void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1483 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1484 void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1485 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1486 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1487 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1488 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1492 inline void ldstub( Register s1, Register s2, Register d );
1493 inline void ldstub( Register s1, int simm13a, Register d);
1497 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1498 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1502 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
1503 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1504 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1505 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1506 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
1507 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1508 void andn( Register s1, RegisterOrConstant s2, Register d);
1509 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1510 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1511 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
1512 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1513 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1514 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1515 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
1516 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1517 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1518 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1519 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
1520 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1521 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1522 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1523 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
1524 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1525 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1526 void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1538 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
1542 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
1543 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
1547 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
1548 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
1552 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
1553 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1554 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
1555 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1556 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
1557 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1561 void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
1562 void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1563 void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
1564 void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1565 void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1566 void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1567 void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1568 void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1572 void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
1573 void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1582 void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1583 void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1587 void prefetch( Register s1, Register s2, PrefetchFcn f);
1588 void prefetch( Register s1, int simm13a, PrefetchFcn f);
1589 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1590 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1598 inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1599 inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1600 inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
1601 inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
1602 inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
1603 inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
1607 inline void rett( Register s1, Register s2);
1608 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1612 void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
1613 void save( Register s1, int simm13a, Register d ) {
1619 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
1620 void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1629 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1632 void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1633 void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1634 void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1635 void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1636 void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1637 void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1639 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1640 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1641 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1642 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1643 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1644 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1656 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
1657 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1658 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1661 inline void stfsr( Register s1, Register s2 );
1662 inline void stfsr( Register s1, int simm13a);
1663 inline void stxfsr( Register s1, Register s2 );
1664 inline void stxfsr( Register s1, int simm13a);
1668 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1669 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1673 inline void stb( Register d, Register s1, Register s2 );
1674 inline void stb( Register d, Register s1, int simm13a);
1675 inline void sth( Register d, Register s1, Register s2 );
1676 inline void sth( Register d, Register s1, int simm13a);
1677 inline void stw( Register d, Register s1, Register s2 );
1678 inline void stw( Register d, Register s1, int simm13a);
1679 inline void st( Register d, Register s1, Register s2 );
1680 inline void st( Register d, Register s1, int simm13a);
1681 inline void stx( Register d, Register s1, Register s2 );
1682 inline void stx( Register d, Register s1, int simm13a);
1683 inline void std( Register d, Register s1, Register s2 );
1684 inline void std( Register d, Register s1, int simm13a);
1688 inline void st( Register d, Register s1, ByteSize simm13a);
1691 inline void stb( Register d, const Address& a, int offset = 0 );
1692 inline void sth( Register d, const Address& a, int offset = 0 );
1693 inline void stw( Register d, const Address& a, int offset = 0 );
1694 inline void stx( Register d, const Address& a, int offset = 0 );
1695 inline void st( Register d, const Address& a, int offset = 0 );
1696 inline void std( Register d, const Address& a, int offset = 0 );
1698 inline void stb( Register d, Register s1, RegisterOrConstant s2 );
1699 inline void sth( Register d, Register s1, RegisterOrConstant s2 );
1700 inline void stw( Register d, Register s1, RegisterOrConstant s2 );
1701 inline void stx( Register d, Register s1, RegisterOrConstant s2 );
1702 inline void std( Register d, Register s1, RegisterOrConstant s2 );
1703 inline void st( Register d, Register s1, RegisterOrConstant s2 );
1707 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1708 void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1709 void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1710 void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1711 void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1712 void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1713 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1714 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1715 void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1716 void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1720 inline void stc( int crd, Register s1, Register s2 );
1721 inline void stc( int crd, Register s1, int simm13a);
1722 inline void stdc( int crd, Register s1, Register s2 );
1723 inline void stdc( int crd, Register s1, int simm13a);
1724 inline void stcsr( int crd, Register s1, Register s2 );
1725 inline void stcsr( int crd, Register s1, int simm13a);
1726 inline void stdcq( int crd, Register s1, Register s2 );
1727 inline void stdcq( int crd, Register s1, int simm13a);
1731 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1732 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1735 inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
1737 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1738 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1739 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
1740 void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1741 void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1742 void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1746 inline void swap( Register s1, Register s2, Register d );
1747 inline void swap( Register s1, int simm13a, Register d);
1748 inline void swap( Address& a, Register d, int offset = 0 );
1752 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1753 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1757 void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
1758 void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1759 void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
1760 void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1764 void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
1765 void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1766 void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
1767 void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1771 void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1772 void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1778 inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1779 inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1780 inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) |
1786 inline void wrasi(Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1788 inline void wrasi(Register d, int simm13a) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1790 inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1795 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1796 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1797 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1799 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_long( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1800 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_long( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1845 static void restore_registers(MacroAssembler* a, Register r);
1875 VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
1895 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1896 Register java_thread_cache, // the thread if computed before ; use noreg otherwise
1897 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1906 virtual void check_and_handle_popframe(Register scratch_reg);
1907 virtual void check_and_handle_earlyret(Register scratch_reg);
1921 void null_check(Register reg, int offset = -1);
1935 void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
1938 void br_null ( Register s1, bool a, Predict p, Label& L );
1939 void br_notnull( Register s1, bool a, Predict p, Label& L );
1948 void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
1949 void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
1951 void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
1952 void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
1955 void br_null_short ( Register s1, Predict p, Label& L );
1956 void br_notnull_short( Register s1, Predict p, Label& L );
1976 inline int get_pc( Register d );
1979 inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
1980 inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
1982 inline void jmp( Register s1, Register s2 );
1983 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1989 inline void callr( Register s1, Register s2 );
1990 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1996 inline void tst( Register s ) { orcc( G0, s, G0 ); }
2023 void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
2025 void sethi(const AddressLiteral& addrlit, Register d);
2026 void patchable_sethi(const AddressLiteral& addrlit, Register d);
2034 void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
2037 void set(const AddressLiteral& addrlit, Register d);
2038 void set(intptr_t value, Register d);
2039 void set(address addr, Register d, RelocationHolder const& rspec);
2042 void patchable_set(const AddressLiteral& addrlit, Register d);
2043 void patchable_set(intptr_t value, Register d);
2044 void set64(jlong value, Register d, Register tmp);
2048 inline void signx( Register s, Register d ) { sra( s, G0, d); }
2049 inline void signx( Register d ) { sra( d, G0, d); }
2051 inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
2052 inline void not1( Register d ) { xnor( d, G0, d ); }
2054 inline void neg( Register s, Register d ) { sub( G0, s, d ); }
2055 inline void neg( Register d ) { sub( G0, d, d ); }
2057 inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
2058 inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
2061 inline void cas_ptr( Register s1, Register s2, Register d) {
2070 inline void sll_ptr( Register s1, Register s2, Register d );
2071 inline void sll_ptr( Register s1, int imm6a, Register d );
2072 inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
2073 inline void srl_ptr( Register s1, Register s2, Register d );
2074 inline void srl_ptr( Register s1, int imm6a, Register d );
2077 inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
2078 inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
2080 inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); }
2081 inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); }
2083 inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); }
2084 inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); }
2086 inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); }
2087 inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); }
2089 inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); }
2090 inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); }
2092 inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); }
2093 inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); }
2095 inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); }
2096 inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); }
2098 inline void clr( Register d ) { or3( G0, G0, d ); }
2100 inline void clrb( Register s1, Register s2);
2101 inline void clrh( Register s1, Register s2);
2102 inline void clr( Register s1, Register s2);
2103 inline void clrx( Register s1, Register s2);
2105 inline void clrb( Register s1, int simm13a);
2106 inline void clrh( Register s1, int simm13a);
2107 inline void clr( Register s1, int simm13a);
2108 inline void clrx( Register s1, int simm13a);
2111 inline void clruw( Register s, Register d ) { srl( s, G0, d); }
2113 inline void clruwu( Register d ) { srl( d, G0, d); }
2122 inline void mov( Register s, Register d) {
2127 inline void mov_or_nop( Register s, Register d) {
2132 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
2135 inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
2136 inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
2137 inline void load_bool_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
2138 inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
2139 inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
2140 inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
2141 inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
2142 inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0);
2143 inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
2147 void jmp2( Register r1, Register r2, const char* file, int line );
2148 void jmp ( Register r1, int offset, const char* file, int line );
2150 void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
2151 void jump (const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line);
2156 inline void load_argument( Argument& a, Register d );
2157 inline void store_argument( Register s, Argument& a );
2158 inline void store_ptr_argument( Register s, Argument& a );
2161 inline void store_long_argument( Register s, Argument& a );
2165 inline void round_to( Register r, int modulus ) {
2176 inline void ld_ptr(Register s1, Register s2, Register d);
2177 inline void ld_ptr(Register s1, int simm13a, Register d);
2178 inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
2179 inline void ld_ptr(const Address& a, Register d, int offset = 0);
2180 inline void st_ptr(Register d, Register s1, Register s2);
2181 inline void st_ptr(Register d, Register s1, int simm13a);
2182 inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
2183 inline void st_ptr(Register d, const Address& a, int offset = 0);
2187 inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
2188 inline void st_ptr(Register d, Register s1, ByteSize simm13a);
2193 inline void ld_long(Register s1, Register s2, Register d);
2194 inline void ld_long(Register s1, int simm13a, Register d);
2195 inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
2196 inline void ld_long(const Address& a, Register d, int offset = 0);
2197 inline void st_long(Register d, Register s1, Register s2);
2198 inline void st_long(Register d, Register s1, int simm13a);
2199 inline void st_long(Register d, Register s1, RegisterOrConstant s2);
2200 inline void st_long(Register d, const Address& a, int offset = 0);
2206 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2207 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2208 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2210 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
2234 void serialize_memory(Register thread, Register tmp1, Register tmp2);
2241 void mult(Register s1, Register s2, Register d);
2242 void mult(Register s1, int simm13a, Register d);
2245 void read_ccr(Register d);
2246 void write_ccr(Register s);
2252 inline void stbool(Register d, const Address& a) { stb(d, a); }
2253 inline void ldbool(const Address& a, Register d) { ldub(a, d); }
2254 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
2257 void load_klass(Register src_oop, Register klass);
2258 void store_klass(Register klass, Register dst_oop);
2259 void store_klass_gap(Register s, Register dst_oop);
2262 void load_heap_oop(const Address& s, Register d);
2263 void load_heap_oop(Register s1, Register s2, Register d);
2264 void load_heap_oop(Register s1, int simm13a, Register d);
2265 void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
2266 void store_heap_oop(Register d, Register s1, Register s2);
2267 void store_heap_oop(Register d, Register s1, int simm13a);
2268 void store_heap_oop(Register d, const Address& a, int offset = 0);
2270 void encode_heap_oop(Register src, Register dst);
2271 void encode_heap_oop(Register r) {
2274 void decode_heap_oop(Register src, Register dst);
2275 void decode_heap_oop(Register r) {
2278 void encode_heap_oop_not_null(Register r);
2279 void decode_heap_oop_not_null(Register r);
2280 void encode_heap_oop_not_null(Register src, Register dst);
2281 void decode_heap_oop_not_null(Register src, Register dst);
2287 void save_thread (const Register threache); // save to cache
2288 void restore_thread(const Register thread_cache); // restore from cache
2291 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
2297 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2298 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
2299 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2300 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2303 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2304 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
2305 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2306 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2308 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
2309 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
2310 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
2311 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
2313 void get_vm_result (Register oop_result);
2314 void get_vm_result_2(Register oop_result);
2317 void set_vm_result(Register oop_result);
2321 void check_and_forward_exception(Register scratch_reg);
2325 void read_ccr_trap(Register ccr_save);
2326 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
2332 void read_ccr_v8_assert(Register ccr_save);
2333 void write_ccr_v8_assert(Register ccr_save);
2339 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
2341 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2345 void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs);
2348 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2372 void _verify_oop(Register reg, const char * msg, const char * file, int line);
2391 inline void set_oop (jobject obj, Register d); // uses allocate_oop_address
2392 inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address
2393 inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address
2395 void set_narrow_oop( jobject obj, Register d );
2422 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
2425 void calc_mem_param_words(Register Rparam_words, Register Rresult);
2429 void calc_frame_size(Register extraWords, Register resultReg);
2432 void calc_frame_size_and_save(Register extraWords, Register resultReg);
2438 void lcmp( Register Ra_hi, Register Ra_low,
2439 Register Rb_hi, Register Rb_low,
2440 Register Rresult);
2442 void lneg( Register Rhi, Register Rlow );
2444 void lshl( Register Rin_high, Register Rin_low, Register Rcount,
2445 Register Rout_high, Register Rout_low, Register Rtemp );
2447 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
2448 Register Rout_high, Register Rout_low, Register Rtemp );
2450 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
2451 Register Rout_high, Register Rout_low, Register Rtemp );
2454 void lcmp( Register Ra, Register Rb, Register Rresult);
2458 void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
2459 void store_sized_value(Register src, Address dst, size_t size_in_bytes);
2463 Register Rresult);
2473 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2475 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2477 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
2481 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
2482 Register Rscratch,
2485 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
2486 Register Rscratch,
2499 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
2508 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
2512 Register obj, // result: pointer to object after successful allocation
2513 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2515 Register t1, // temp register
2516 Register t2, // temp register
2520 Register obj, // result: pointer to object after successful allocation
2521 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2523 Register t1, // temp register
2528 Register t1, Register t2);
2531 void lookup_interface_method(Register recv_klass,
2532 Register intf_klass,
2534 Register method_result,
2535 Register temp_reg, Register temp2_reg,
2539 void lookup_virtual_method(Register recv_klass,
2541 Register method_result);
2550 void check_klass_subtype_fast_path(Register sub_klass,
2551 Register super_klass,
2552 Register temp_reg,
2553 Register temp2_reg,
2564 void check_klass_subtype_slow_path(Register sub_klass,
2565 Register super_klass,
2566 Register temp_reg,
2567 Register temp2_reg,
2568 Register temp3_reg,
2569 Register temp4_reg,
2575 void check_klass_subtype(Register sub_klass,
2576 Register super_klass,
2577 Register temp_reg,
2578 Register temp2_reg,
2585 Register temp_reg,
2589 Register temp_reg = noreg,
2604 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
2606 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
2614 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
2616 void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
2617 void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2);
2620 void char_arrays_equals(Register ary1, Register ary2,
2621 Register limit, Register result,
2622 Register chr1, Register chr2, Label& Ldone);
2624 void bis_zeroing(Register to, Register count, Register temp, Label& Ldone);
2645 SkipIfEqual(MacroAssembler*, Register temp,