Lines Matching refs:Ralt_count
2303 Register Ralt_count = Rtemp;
2306 assert( Ralt_count != Rin_high
2307 && Ralt_count != Rin_low
2308 && Ralt_count != Rcount
2322 subcc(Rcount, 31, Ralt_count);
2324 delayed()->dec(Ralt_count);
2326 // shift < 32 bits, Ralt_count = Rcount-31
2333 neg(Ralt_count);
2338 srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count
2350 // shift >= 32 bits, Ralt_count = Rcount-32
2352 sll(Rin_low, Ralt_count, Rout_high );
2364 Register Ralt_count = Rtemp;
2367 assert( Ralt_count != Rin_high
2368 && Ralt_count != Rin_low
2369 && Ralt_count != Rcount
2383 subcc(Rcount, 31, Ralt_count);
2385 delayed()->dec(Ralt_count);
2387 // shift < 32 bits, Ralt_count = Rcount-31
2394 neg(Ralt_count);
2402 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
2411 // shift >= 32 bits, Ralt_count = Rcount-32
2414 sra(Rin_high, Ralt_count, Rout_low);
2427 Register Ralt_count = Rtemp;
2430 assert( Ralt_count != Rin_high
2431 && Ralt_count != Rin_low
2432 && Ralt_count != Rcount
2446 subcc(Rcount, 31, Ralt_count);
2448 delayed()->dec(Ralt_count);
2450 // shift < 32 bits, Ralt_count = Rcount-31
2457 neg(Ralt_count);
2465 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
2474 // shift >= 32 bits, Ralt_count = Rcount-32
2477 srl(Rin_high, Ralt_count, Rout_low);