Lines Matching defs:Rout_low
2299 Register Rout_high, Register Rout_low,
2312 && Rxfer_bits != Rout_low
2313 && Rout_low != Rin_high,
2339 if (Rcount != Rout_low) {
2340 sll(Rin_low, Rcount, Rout_low); // low half
2343 if (Rcount == Rout_low) {
2344 sll(Rin_low, Rcount, Rout_low); // low half
2353 clr(Rout_low);
2361 Register Rout_high, Register Rout_low,
2395 if (Rcount != Rout_low) {
2396 srl(Rin_low, Rcount, Rout_low);
2405 if (Rcount == Rout_low) {
2406 srl(Rin_low, Rcount, Rout_low);
2409 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
2414 sra(Rin_high, Ralt_count, Rout_low);
2424 Register Rout_high, Register Rout_low,
2458 if (Rcount != Rout_low) {
2459 srl(Rin_low, Rcount, Rout_low);
2468 if (Rcount == Rout_low) {
2469 srl(Rin_low, Rcount, Rout_low);
2472 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
2477 srl(Rin_high, Ralt_count, Rout_low);