Lines Matching refs:g6
63 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
78 mov %g6, %g2 ! arg2 = tagaccess
107 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SN1)
108 CPU_PADDR(%g5, %g6)
110 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
111 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
112 stna %sp, [%g6 + MPCB_SPBUF]%asi
115 sta %g5, [%g6 + MPCB_WBCNT]%asi
124 FAULT_WINTRACE(%g5, %g6, %g1, TT_F32_SO0)
133 CPU_ADDR(%g5, %g6)
160 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
161 CPU_PADDR(%g5, %g6)
166 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
167 lda [%g6 + MPCB_WBCNT]%asi, %g5
169 sta %g7, [%g6 + MPCB_WBCNT]%asi
174 add %g6, %g7, %g7
177 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
199 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
214 mov %g6, %g2 ! arg2 = tagaccess
243 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_SN1)
244 CPU_PADDR(%g5, %g6)
246 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
247 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
248 stna %sp, [%g6 + MPCB_SPBUF]%asi
251 sta %g5, [%g6 + MPCB_WBCNT]%asi
264 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_NT1)
265 CPU_PADDR(%g5, %g6)
266 set CPU_KWBUF_SP, %g6
267 add %g5, %g6, %g6
269 stna %sp, [%g6]%asi
270 set CPU_KWBUF, %g6
271 add %g5, %g6, %g6
272 SAVE_V8WINDOW_ASI(%g6)
273 mov 1, %g6
281 sta %g6, [%g5 + MCPU_KWBUF_FULL]%asi
293 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_NT1)
294 CPU_PADDR(%g5, %g6)
295 set CPU_KWBUF_SP, %g6
296 add %g5, %g6, %g6
298 stna %sp, [%g6]%asi
299 set CPU_KWBUF, %g6
300 add %g5, %g6, %g6
301 SAVE_V9WINDOW_ASI(%g6)
302 mov 1, %g6
310 sta %g6, [%g5 + MCPU_KWBUF_FULL]%asi
317 FAULT_WINTRACE(%g5, %g6, %g1, TT_F64_SO0)
326 CPU_ADDR(%g5, %g6)
353 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_SO1)
354 CPU_PADDR(%g5, %g6)
359 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
360 lda [%g6 + MPCB_WBCNT]%asi, %g5
362 sta %g7, [%g6 + MPCB_WBCNT]%asi
367 add %g6, %g7, %g7
370 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
399 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
403 mov %g6, %g2 ! arg2 = tagaccess
456 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
460 mov %g6, %g2 ! arg2 = tagaccess
479 mov MMU_PCONTEXT, %g6
480 stxa %g5, [%g6]ASI_MMU_CTX