Lines Matching refs:g5
63 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
64 ! sfar (g5 == T_ALIGNMENT)
80 cmp %g5, T_ALIGNMENT
91 rdpr %tstate, %g5
92 and %g5, TSTATE_CWP, %g5
94 wrpr %g0, %g5, %cwp
107 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SN1)
108 CPU_PADDR(%g5, %g6)
110 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
111 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
113 SAVE_V8WINDOW_ASI(%g5)
114 mov 1, %g5
115 sta %g5, [%g6 + MPCB_WBCNT]%asi
117 set sys_trap, %g5
118 wrpr %g5, %tnpc
124 FAULT_WINTRACE(%g5, %g6, %g1, TT_F32_SO0)
133 CPU_ADDR(%g5, %g6)
134 ldn [%g5 + CPU_MPCB], %g1
160 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
161 CPU_PADDR(%g5, %g6)
166 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
167 lda [%g6 + MPCB_WBCNT]%asi, %g5
168 add %g5, 1, %g7
173 sll %g5, CPTRSHIFT, %g7 ! spbuf size is sizeof (caddr_t)
176 sll %g5, RWIN32SHIFT, %g7
177 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
178 add %g5, %g7, %g7
181 set sys_trap, %g5
182 wrpr %g5, %tnpc
199 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
200 ! sfar (g5 == T_ALIGNMENT)
215 mov %g5, %g3 ! arg3 = traptype
216 cmp %g5, T_ALIGNMENT
227 rdpr %tstate, %g5
228 and %g5, TSTATE_CWP, %g5
230 wrpr %g0, %g5, %cwp
243 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_SN1)
244 CPU_PADDR(%g5, %g6)
246 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
247 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
249 SAVE_V9WINDOW_ASI(%g5)
250 mov 1, %g5
251 sta %g5, [%g6 + MPCB_WBCNT]%asi
253 set sys_trap, %g5
254 wrpr %g5, %tnpc
264 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_NT1)
265 CPU_PADDR(%g5, %g6)
267 add %g5, %g6, %g6
271 add %g5, %g6, %g6
274 add %g5, CPU_MCPU, %g5
276 lda [%g5 + MCPU_KWBUF_FULL]%asi, %g7
281 sta %g6, [%g5 + MCPU_KWBUF_FULL]%asi
293 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_NT1)
294 CPU_PADDR(%g5, %g6)
296 add %g5, %g6, %g6
300 add %g5, %g6, %g6
303 add %g5, CPU_MCPU, %g5
305 lda [%g5 + MCPU_KWBUF_FULL]%asi, %g7
310 sta %g6, [%g5 + MCPU_KWBUF_FULL]%asi
317 FAULT_WINTRACE(%g5, %g6, %g1, TT_F64_SO0)
326 CPU_ADDR(%g5, %g6)
327 ldn [%g5 + CPU_MPCB], %g1
353 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_SO1)
354 CPU_PADDR(%g5, %g6)
359 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
360 lda [%g6 + MPCB_WBCNT]%asi, %g5
361 add %g5, 1, %g7
366 sll %g5, CPTRSHIFT, %g7 ! spbuf size is sizeof (caddr_t)
369 sll %g5, RWIN64SHIFT, %g7
370 ldxa [%g6 + MPCB_WBUF_PA]%asi, %g5
371 add %g5, %g7, %g7
374 set sys_trap, %g5
375 wrpr %g5, %tnpc
399 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
400 ! sfar (g5 == T_ALIGNMENT)
405 cmp %g5, T_ALIGNMENT
416 rdpr %tstate, %g5
417 and %g5, TSTATE_CWP, %g5
419 wrpr %g0, %g5, %cwp
456 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
457 ! sfar (g5 == T_ALIGNMENT)
462 cmp %g5, T_ALIGNMENT
478 mov KCONTEXT, %g5
480 stxa %g5, [%g6]ASI_MMU_CTX