Lines Matching refs:g1
52 FAULT_WINTRACE(%g1, %g2, %g3, TT_F32_SN0)
66 CPU_ADDR(%g4, %g1)
67 ldn [%g4 + CPU_MPCB], %g1
68 stn %sp, [%g1 + MPCB_SPBUF]
69 ldn [%g1 + MPCB_WBUF], %g2
72 st %g2, [%g1 + MPCB_WBCNT]
77 set sfmmu_tsbmiss_exception, %g1
83 set trap, %g1
124 FAULT_WINTRACE(%g5, %g6, %g1, TT_F32_SO0)
134 ldn [%g5 + CPU_MPCB], %g1
135 ld [%g1 + MPCB_WBCNT], %g2
137 st %g3, [%g1 + MPCB_WBCNT]
142 add %g1, MPCB_SPBUF, %g3
145 ldn [%g1 + MPCB_WBUF], %g3
188 FAULT_WINTRACE(%g1, %g2, %g3, TT_F64_SN0)
202 CPU_ADDR(%g4, %g1)
203 ldn [%g4 + CPU_MPCB], %g1
204 stn %sp, [%g1 + MPCB_SPBUF]
205 ldn [%g1 + MPCB_WBUF], %g2
208 st %g2, [%g1 + MPCB_WBCNT]
213 set sfmmu_tsbmiss_exception, %g1
219 set trap, %g1
279 mov PTL1_BAD_WTRAP, %g1
308 mov PTL1_BAD_WTRAP, %g1
317 FAULT_WINTRACE(%g5, %g6, %g1, TT_F64_SO0)
327 ldn [%g5 + CPU_MPCB], %g1
328 ld [%g1 + MPCB_WBCNT], %g2
330 st %g3, [%g1 + MPCB_WBCNT]
335 add %g1, MPCB_SPBUF, %g3
338 ldn [%g1 + MPCB_WBUF], %g3
387 FAULT_WINTRACE(%g1, %g2, %g3, TT_F32_FN0)
402 set sfmmu_tsbmiss_exception, %g1
408 set trap, %g1
424 FAULT_WINTRACE(%g1, %g2, %g3, TT_F32_FN1)
439 rdpr %tstate, %g1
440 and %g1, TSTATE_CWP, %g1
441 wrpr %g0, %g1, %cwp
447 set TSTATE_KERN | TSTATE_IE, %g1
448 wrpr %g0, %g1, %tstate
449 set user_rtt, %g1
450 wrpr %g0, %g1, %tpc
451 add %g1, 4, %g1
452 wrpr %g0, %g1, %tnpc
459 set sfmmu_tsbmiss_exception, %g1
465 set trap, %g1
488 FAULT_WINTRACE(%g1, %g2, %g3, TT_F64_FN0)
494 FAULT_WINTRACE(%g1, %g2, %g3, TT_F64_FN1)
501 FAULT_WINTRACE(%g1, %g2, %g3, TT_RTT_FN1)
513 mov PTL1_BAD_WTRAP, %g1