Lines Matching refs:g4
84 * %g4 desire %pil
129 sub %g0, 1, %g4 ;\
165 sub %g0, 1, %g4 ;\
184 sub %g0, 1, %g4 ;\
234 sub %g0, 1, %g4 ;\
245 sub %g0, 1, %g4 ;\
252 sub %g0, 1, %g4 ;\
338 add %sp, 16, %g4 ;\
339 sta %l4, [%g4 + %g0]asi_num ;\
340 sta %l5, [%g4 + %g1]asi_num ;\
341 sta %l6, [%g4 + %g2]asi_num ;\
342 sta %l7, [%g4 + %g3]asi_num ;\
343 add %g4, 16, %g4 ;\
344 sta %i0, [%g4 + %g0]asi_num ;\
345 sta %i1, [%g4 + %g1]asi_num ;\
346 sta %i2, [%g4 + %g2]asi_num ;\
347 sta %i3, [%g4 + %g3]asi_num ;\
348 add %g4, 16, %g4 ;\
349 sta %i4, [%g4 + %g0]asi_num ;\
350 sta %i5, [%g4 + %g1]asi_num ;\
351 sta %i6, [%g4 + %g2]asi_num ;\
352 sta %i7, [%g4 + %g3]asi_num ;\
414 add %sp, 16, %g4 ;\
415 lda [%g4 + %g0]asi_num, %l4 ;\
416 lda [%g4 + %g1]asi_num, %l5 ;\
417 lda [%g4 + %g2]asi_num, %l6 ;\
418 lda [%g4 + %g3]asi_num, %l7 ;\
419 add %g4, 16, %g4 ;\
420 lda [%g4 + %g0]asi_num, %i0 ;\
421 lda [%g4 + %g1]asi_num, %i1 ;\
422 lda [%g4 + %g2]asi_num, %i2 ;\
423 lda [%g4 + %g3]asi_num, %i3 ;\
424 add %g4, 16, %g4 ;\
425 lda [%g4 + %g0]asi_num, %i4 ;\
426 lda [%g4 + %g1]asi_num, %i5 ;\
427 lda [%g4 + %g2]asi_num, %i6 ;\
428 lda [%g4 + %g3]asi_num, %i7 ;\
491 mov 24 + V9BIAS64, %g4 ;\
492 stxa %l3, [%sp + %g4]asi_num ;\
497 stxa %l7, [%g5 + %g4]asi_num ;\
502 stxa %i3, [%g5 + %g4]asi_num ;\
507 stxa %i7, [%g5 + %g4]asi_num ;\
563 mov V9BIAS64 + 24, %g4 ;\
564 ldxa [%sp + %g4]asi_num, %l3 ;\
569 ldxa [%g5 + %g4]asi_num, %l7 ;\
574 ldxa [%g5 + %g4]asi_num, %i3 ;\
579 ldxa [%g5 + %g4]asi_num, %i7 ;\
650 add %sp, 16, %g4 ;\
651 sta %l4, [%g4 + %g0]asi_num ;\
652 sta %l5, [%g4 + %g1]asi_num ;\
653 sta %l6, [%g4 + %g2]asi_num ;\
654 sta %l7, [%g4 + %g3]asi_num ;\
655 add %g4, 16, %g4 ;\
656 sta %i0, [%g4 + %g0]asi_num ;\
657 sta %i1, [%g4 + %g1]asi_num ;\
658 sta %i2, [%g4 + %g2]asi_num ;\
659 sta %i3, [%g4 + %g3]asi_num ;\
660 add %g4, 16, %g4 ;\
661 sta %i4, [%g4 + %g0]asi_num ;\
662 sta %i5, [%g4 + %g1]asi_num ;\
663 sta %i6, [%g4 + %g2]asi_num ;\
664 sta %i7, [%g4 + %g3]asi_num ;\
679 mov 24 + V9BIAS64, %g4 ;\
680 stxa %l3, [%sp + %g4]asi_num ;\
685 stxa %l7, [%g5 + %g4]asi_num ;\
690 stxa %i3, [%g5 + %g4]asi_num ;\
695 stxa %i7, [%g5 + %g4]asi_num ;\
740 sub %g0, 1, %g4 ;\
753 sethi %hi(.check_v9utrap), %g4 ;\
754 jmp %g4 + %lo(.check_v9utrap) ;\
765 sethi %hi(.check_v9utrap), %g4 ;\
766 jmp %g4 + %lo(.check_v9utrap) ;\
777 sethi %hi(.check_v9utrap), %g4 ;\
778 jmp %g4 + %lo(.check_v9utrap) ;\
788 sethi %hi(.check_v9utrap), %g4 ;\
789 jmp %g4 + %lo(.check_v9utrap) ;\
802 mov level, %g4 ;\
807 mov PIL_14, %g4 ;\
812 mov PIL_15, %g4 ;\
953 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\
997 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\
1043 * g3 - g4 = scratch (clobbered)
1055 GET_TRACE_TICK(%g6, %g4) ;\
1069 MMU_FAULT_STATUS_AREA(%g4) ;\
1075 ldx [%g4 + %g1], %g1 ;\
1082 ldx [%g4 + %g1], %g1 ;\
1084 TRACE_NEXT(%g3, %g4, %g6)
1389 * g3 - g4 = scratch (clobbered)
1400 MMU_FAULT_STATUS_AREA(%g4)
1401 ldx [%g4 + MMFSA_I_ADDR], %g2 /* g2 = address */
1402 ldx [%g4 + MMFSA_I_CTX], %g3 /* g3 = ctx */
1411 mov -1, %g4
1419 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1445 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1458 CPU_INDEX(%g4, %g5)
1460 sllx %g4, CPU_CORE_SHIFT, %g4
1461 add %g4, %g5, %g4
1462 lduh [%g4 + CPUC_DTRACE_FLAGS], %g5
1466 stuh %g5, [%g4 + CPUC_DTRACE_FLAGS]
1474 sub %g0, 1, %g4
1477 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1479 rdpr %tstate, %g4
1480 btst TSTATE_PRIV, %g4
1502 sub %g0, 1, %g4
1509 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1523 sub %g0, 1, %g4
1533 sub %g0, 1, %g4 ! the save instruction below
1542 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1558 rdpr %cwp, %g4
1560 wrpr %g1, %g4, %tstate
1570 CPU_ADDR(%g4, %g1) ! load CPU struct addr
1571 ldn [%g4 + CPU_THREAD], %g5 ! load thread pointer
1594 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR
1597 st %g0, [%g4 + CPU_TL1_HDLR] ! clr CPU_TL1_HDLR
1599 sethi %hi(0xc1c00000), %g4 ! setup mask for illtrap instruction
1600 andcc %g1, %g4, %g4 ! and instruction with mask
1601 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP
1610 sub %g0, 1, %g4
1620 sub %g0, 1, %g4 ! the save instruction below
1629 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1643 rdpr %cwp, %g4
1645 wrpr %g2, %g4, %tstate
1647 ldn [%g1 + T_PROCP], %g4 ! load proc pointer
1648 ldn [%g4 + P_AS], %g4 ! load as pointer
1649 ldn [%g4 + A_USERLIMIT], %g4 ! load as userlimit
1650 cmp %l7, %g4 ! check for single-step set
1654 ld [%g1 + PCB_STEP], %g4 ! load single-step flag
1655 cmp %g4, STEP_ACTIVE ! step flags set in pcb?
1659 mov %l7, %g4 ! on entry to precise user trap
1662 wrpr %g0, %g4, %tnpc ! generate FLTBOUNDS,
1663 ! %g4 == userlimit
1672 CPU_ADDR(%g1, %g4)
1748 set _fitos_fitod_table, %g4
1750 jmp %g4 + %g7
1794 set _fitos_fdtos_table, %g4
1796 jmp %g4 + %g7
1875 sub %g0, 1, %g4
1890 sub %g0, 1, %g4
2077 CPU_ADDR(%g1, %g4)
2078 or %g0, 1, %g4
2079 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2119 LDDF_REG(%g3, %g7, %g4)
2121 CPU_ADDR(%g1, %g4)
2125 CPU_ADDR(%g1, %g4)
2133 sub %g0, 1, %g4
2145 CPU_ADDR(%g1, %g4)
2146 or %g0, 1, %g4
2147 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2174 STDF_REG(%g6, %g7, %g4) ! STDF_REG(REG, ADDR, TMP)
2182 CPU_ADDR(%g1, %g4)
2186 CPU_ADDR(%g1, %g4)
2194 sub %g0, 1, %g4
2199 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2201 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2210 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2212 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2297 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef
2298 wr %g0, %g4, %fprs ! write fprs
2304 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs
2305 srlx %g4, 2, %g4 ! shift fef value to bit 0
2306 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en
2538 ldx [%g6 + MMFSA_D_ADDR], %g4
2539 stxa %g4, [%g3 + TRAP_ENT_TR]%asi
2540 ldx [%g6 + MMFSA_D_CTX], %g4
2541 stxa %g4, [%g3 + TRAP_ENT_F1]%asi
2542 ldx [%g6 + MMFSA_D_TYPE], %g4
2543 stxa %g4, [%g3 + TRAP_ENT_F2]%asi
2546 TRACE_NEXT(%g3, %g4, %g5)
2563 ldx [%g6 + MMFSA_I_ADDR], %g4
2564 stxa %g4, [%g3 + TRAP_ENT_TR]%asi
2565 ldx [%g6 + MMFSA_I_CTX], %g4
2566 stxa %g4, [%g3 + TRAP_ENT_F1]%asi
2567 ldx [%g6 + MMFSA_I_TYPE], %g4
2568 stxa %g4, [%g3 + TRAP_ENT_F2]%asi
2571 TRACE_NEXT(%g3, %g4, %g5)
2592 TRACE_NEXT(%g3, %g4, %g5)
2608 * g3 - g4 = scratch (clobbered)
2626 * g4 = tsbe tag (in/clobbered)
2637 stna %g4, [%g5 + TRAP_ENT_F1]%asi ! XXX? tsb tag
2638 GET_TRACE_TICK(%g6, %g4)
2647 or %g6, TT_MMU_MISS, %g4
2648 stha %g4, [%g5 + TRAP_ENT_TT]%asi
2649 mov MMFSA_D_ADDR, %g4
2651 move %xcc, MMFSA_I_ADDR, %g4
2653 move %xcc, MMFSA_I_ADDR, %g4
2655 ldx [%g6 + %g4], %g6
2657 cmp %g4, MMFSA_D_ADDR
2658 move %xcc, MMFSA_D_CTX, %g4
2659 movne %xcc, MMFSA_I_CTX, %g4
2661 ldx [%g6 + %g4], %g6
2664 TRACE_NEXT(%g5, %g4, %g6)
2677 GET_TRACE_TICK(%g6, %g4)
2691 mov MMFSA_D_CTX, %g4
2693 move %xcc, MMFSA_I_CTX, %g4
2695 move %xcc, MMFSA_I_CTX, %g4
2697 ldx [%g6 + %g4], %g6
2699 TRACE_NEXT(%g1, %g4, %g5)
2758 ldx [%g3 + MMFSA_D_CTX], %g4
2761 sllx %g4, SFSR_CTX_SHIFT, %g3
2763 cmp %g4, USER_CONTEXT_TYPE
2764 movgeu %icc, USER_CONTEXT_TYPE, %g4
2765 or %g2, %g4, %g2 /* TAG_ACCESS */
2848 mov -1, %g4