Lines Matching refs:g2
83 * %g2, %g3 args for above
334 mov 8, %g2 ;\
335 sta %l2, [%sp + %g2]asi_num ;\
341 sta %l6, [%g4 + %g2]asi_num ;\
346 sta %i2, [%g4 + %g2]asi_num ;\
351 sta %i6, [%g4 + %g2]asi_num ;\
409 mov 8, %g2 ;\
412 lda [%sp + %g2]asi_num, %l2 ;\
417 lda [%g4 + %g2]asi_num, %l6 ;\
422 lda [%g4 + %g2]asi_num, %i2 ;\
427 lda [%g4 + %g2]asi_num, %i6 ;\
487 mov 8 + V9BIAS64, %g2 ;\
488 stxa %l1, [%sp + %g2]asi_num ;\
495 stxa %l5, [%g5 + %g2]asi_num ;\
500 stxa %i1, [%g5 + %g2]asi_num ;\
505 stxa %i5, [%g5 + %g2]asi_num ;\
559 mov V9BIAS64 + 8, %g2 ;\
560 ldxa [%sp + %g2]asi_num, %l1 ;\
567 ldxa [%g5 + %g2]asi_num, %l5 ;\
572 ldxa [%g5 + %g2]asi_num, %i1 ;\
577 ldxa [%g5 + %g2]asi_num, %i5 ;\
646 mov 8, %g2 ;\
647 sta %l2, [%sp + %g2]asi_num ;\
653 sta %l6, [%g4 + %g2]asi_num ;\
658 sta %i2, [%g4 + %g2]asi_num ;\
663 sta %i6, [%g4 + %g2]asi_num ;\
675 mov 8 + V9BIAS64, %g2 ;\
676 stxa %l1, [%sp + %g2]asi_num ;\
683 stxa %l5, [%g5 + %g2]asi_num ;\
688 stxa %i1, [%g5 + %g2]asi_num ;\
693 stxa %i5, [%g5 + %g2]asi_num ;\
751 or %g0, P_UTRAP4, %g2 ;\
763 or %g0, P_UTRAP10, %g2 ;\
775 or %g0, P_UTRAP11, %g2 ;\
851 rdpr %tpc, %g2 ;\
861 * synthesize for trap(): TAG_ACCESS in %g2, SFSR in %g3
868 * synthesize for trap(): SFAR in %g2, SFSR in %g3
872 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\
882 * synthesize for trap(): SFAR in %g2, SFSR in %g3
886 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\
899 * synthesize for trap(): SFAR in %g2, SFSR in %g3
905 * synthesize for trap(): SFAR in %g2, SFSR in %g3
939 * synthesize for miss handler: pseudo-tag access in %g2 (with context "type"
945 GET_MMU_D_PTAGACC_CTXTYPE(%g2, %g3) /* 8 instr */ ;\
948 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
953 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\
955 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
983 * synthesize for miss handler: TAG_ACCESS in %g2 (with context "type"
989 GET_MMU_I_PTAGACC_CTXTYPE(%g2, %g3) /* 8 instr */ ;\
992 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
997 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\
999 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1015 * synthesize for miss handler: TAG_ACCESS in %g2 (with context "type"
1019 GET_MMU_D_PTAGACC_CTXTYPE(%g2, %g3) /* 8 instr */ ;\
1021 * g2 = pseudo-tag access register (ctx type rather than ctx ID) ;\
1042 * g2 = tag access register (in)
1057 stna %g2, [%g3 + TRAP_ENT_SP]%asi /* tag access */ ;\
1388 * g2 = tag access register (in)
1395 * synthesize for miss handler: TAG_ACCESS in %g2 (with context "type"
1401 ldx [%g4 + MMFSA_I_ADDR], %g2 /* g2 = address */
1403 srlx %g2, MMU_PAGESHIFT, %g2 ! align address to page boundry
1405 sllx %g2, MMU_PAGESHIFT, %g2
1407 or %g2, %g3, %g2 /* TAG_ACCESS */
1414 /* %g2 = sfar, %g3 = sfsr */
1435 or %g2, %g0, %g7
1511 ldx [%g1 + CPU_TMP1], %g2
1544 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1546 brz,pt %g2, 1f
1549 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1551 brz,pt %g2, 1f
1553 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1584 smul %g1, CPTRSIZE, %g2
1604 ldn [%g5 + %g2], %g5
1631 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1633 brz,pt %g2, 1f
1636 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1638 brz,pt %g2, 1f
1640 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1642 rdpr %tstate, %g2 ! cwp for trap handler
1644 bclr TSTATE_CWP_MASK, %g2
1645 wrpr %g2, %g4, %tstate
1674 ldx [%g1 + CPU_TMP1], %g2
1690 * %g2 %fsr
1707 srl %g2, FSR_FTT_SHIFT, %g7 ! extract ftt from %fsr
1712 andcc %g2, %g5, %g0
1870 * Note that we need to pass %fsr in %g2 (already read above).
1919 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
1922 mov 1, %g2
1923 stb %g2, [%g1 + P_FIXALIGNMENT]
2069 /* %g2 = sfar, %g3 = sfsr */
2070 mov %g2, %g5 ! stash sfar
2072 sethi %hi(fpu_exists), %g2 ! check fpu_exists
2073 ld [%g2 + %lo(fpu_exists)], %g2
2074 brz,a,pn %g2, 4f
2081 rdpr %tpc, %g2
2082 lda [%g2]ASI_AIUP, %g6 ! get the user's lddf instruction
2089 rdpr %tstate, %g2 ! %tstate in %g2
2091 srl %g2, 31, %g1 ! get asi from %tstate
2130 mov %g5, %g2 ! misaligned vaddr in %g2
2136 /* %g2 = sfar, %g3 = sfsr */
2137 mov %g2, %g5
2149 rdpr %tpc, %g2
2150 lda [%g2]ASI_AIUP, %g6 ! get the user's stdf instruction
2158 rdpr %tstate, %g2 ! %tstate in %g2
2160 srl %g2, 31, %g1 ! get asi from %tstate
2191 mov %g5, %g2 ! misaligned vaddr in %g2
2199 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2201 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2203 mov 1, %g2
2204 st %g2, [%g1]
2210 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2212 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2218 CPU_ADDR(%g1, %g2)
2222 set PSR_ICC, %g2
2223 and %o0, %g2, %o0 ! mask out the rest
2229 CPU_ADDR(%g1, %g2)
2234 CPU_ADDR(%g1, %g2)
2240 CPU_ADDR(%g1, %g2)
2241 sll %o0, PSR_ICC_SHIFT, %g2
2243 and %g2, %g3, %g2 ! mask out rest
2244 sllx %g2, PSR_TSTATE_CC_SHIFT, %g2
2247 or %g3, %g2, %g3 ! or in new bits
2264 set PSR_ICC, %g2
2265 and %o0, %g2, %o0 ! mask out the rest
2268 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower
2269 sllx %g2, PSR_FPRS_FEF_SHIFT, %g2 ! shift fef to V8 psr.ef
2270 or %o0, %g2, %o0 ! or result into psr.ef
2272 set V9_PSR_IMPLVER, %g2 ! SI assigned impl/ver: 0xef
2273 or %o0, %g2, %o0 ! or psr.impl/ver
2285 ! setx TSTATE_V8_UBITS, %g2
2287 sllx %g3, TSTATE_CCR_SHIFT, %g2
2289 andn %g1, %g2, %g1 ! zero current user bits
2290 set PSR_ICC, %g2
2291 and %g2, %o0, %g2 ! clear all but psr.icc bits
2292 sllx %g2, PSR_TSTATE_CC_SHIFT, %g3 ! shift to tstate.ccr.icc
2295 set PSR_EF, %g2
2296 and %g2, %o0, %g2 ! clear all but fp enable bit
2297 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef
2300 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1
2301 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2302 ldn [%g2 + T_LWP], %g3 ! load klwp pointer
2303 ldn [%g3 + LWP_FPU], %g2 ! get lwp_fpu pointer
2304 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs
2306 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en
2317 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2319 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2320 ldn [%g2 + T_LPL], %g2 ! load lpl pointer
2321 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid
2330 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2331 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2332 ldn [%g2 + T_LWP], %g2 ! load klwp pointer
2333 ld [%g2 + PCB_TRAP0], %g2 ! lwp->lwp_pcb.pcb_trap0addr
2334 brz,pn %g2, 1f ! has it been set?
2338 wrpr %g0, %g2, %tnpc ! setup tnpc
2367 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2375 ldn [%l0 + CPU_THREAD], %g2 ! load thread pointer
2376 ldn [%g2 + T_LWP], %g2 ! load klwp pointer
2378 st %l1, [%g2 + PCB_TRAP0] ! lwp->lwp_pcb.pcb_trap0addr
2607 * g2 = tag access register (in)
2624 * g2 = tag access register (in)
2636 stna %g2, [%g5 + TRAP_ENT_SP]%asi ! tag access
2669 * g2 = tag access register (in)
2683 stna %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg
2714 setx ptl1_panic, %g2, %o1
2720 * synthesize for trap(): SFAR in %g2, SFSR in %g3
2725 ldx [%g3 + MMFSA_D_ADDR], %g2
2737 * synthesize for trap(): SFAR in %g2, SFSR in %g3
2742 ldx [%g3 + MMFSA_D_ADDR], %g2
2756 ldx [%g3 + MMFSA_D_ADDR], %g2
2759 srlx %g2, MMU_PAGESHIFT, %g2 /* align address */
2760 sllx %g2, MMU_PAGESHIFT, %g2
2765 or %g2, %g4, %g2 /* TAG_ACCESS */
2865 CPU_ADDR(%g2, %g1) /* load CPU struct addr to %g2 */ ;\
2866 ldn [%g2 + CPU_THREAD], %g3 /* load thread pointer */ ;\
2881 * %g2: address of CPU structure \