Lines Matching refs:g4
70 ! %g4 queue size mask
75 mov CPU_MONDO_Q_TL, %g4
76 ldxa [%g4]ASI_QUEUE, %g7 ! %g7 = tail ptr
84 ldx [%g2 + MCPU_CPU_Q_SIZE], %g4 ! queue size
85 sub %g4, 1, %g4 ! %g4 = queue size mask
104 and %g6, %g4, %g6 ! and size mask for wrap around
110 TRACE_PTR(%g4, %g6)
112 stxa %g6, [%g4 + TRAP_ENT_TICK]%asi
113 TRACE_SAVE_TL_GL_REGS(%g4, %g6)
115 stha %g6, [%g4 + TRAP_ENT_TT]%asi
117 stna %g6, [%g4 + TRAP_ENT_TPC]%asi
119 stxa %g6, [%g4 + TRAP_ENT_TSTATE]%asi
120 stna %sp, [%g4 + TRAP_ENT_SP]%asi
121 stna %g5, [%g4 + TRAP_ENT_TR]%asi ! pc of the TL>0 handler
122 stna %g1, [%g4 + TRAP_ENT_F1]%asi ! arg1
123 stna %g2, [%g4 + TRAP_ENT_F3]%asi ! arg2
126 stna %g6, [%g4 + TRAP_ENT_F2]%asi
127 stna %g7, [%g4 + TRAP_ENT_F4]%asi ! tail offset
128 TRACE_NEXT(%g4, %g6, %g3)
134 set KERNELBASE, %g4
135 cmp %g5, %g4
154 set OFW_START_ADDR, %g4 ! Check if this a call into OBP?
155 cmp %g5, %g4
158 set OFW_END_ADDR, %g4
159 cmp %g5, %g4
163 ldxa [%g3]ASI_MMU_CTX, %g4
164 cmp %g4, INVALID_CONTEXT ! Check if we are in kernel mode
167 set INVALID_CONTEXT, %g4 ! Invalidate contexts - compatability
168 stxa %g4, [%g3]ASI_MMU_CTX ! mode ensures shared contexts are also
170 stxa %g4, [%g3]ASI_MMU_CTX
173 mov %o1, %g4
182 mov %g4, %o1
189 set cpu_mondo_inval, %g4
190 ldx [%g4], %g5
192 stx %g5, [%g4]
224 ! %g4 queue size mask
229 mov DEV_MONDO_Q_TL, %g4
230 ldxa [%g4]ASI_QUEUE, %g7 ! %g7 = tail ptr
249 set MAXIVNUM, %g4
250 cmp %g5, %g4
252 ldx [%g2 + MCPU_DEV_Q_SIZE], %g4 ! queue size - delay slot
270 ldx [%g2 + MCPU_DEV_Q_SIZE], %g4 ! queue size - delay slot
274 ldx [%g2 + MCPU_DEV_Q_SIZE], %g4 ! queue size - delay slot
280 ldxa [%g3 + %g7]ASI_MEM, %g4
281 stx %g4, [%g1 + 0] ! byte 0 - 7
283 ldxa [%g3 + %g7]ASI_MEM, %g4
284 stx %g4, [%g1 + 8] ! byte 8 - 15
286 ldxa [%g3 + %g7]ASI_MEM, %g4
287 stx %g4, [%g1 + 16] ! byte 16 - 23
289 ldxa [%g3 + %g7]ASI_MEM, %g4
290 stx %g4, [%g1 + 24] ! byte 24 - 31
292 ldxa [%g3 + %g7]ASI_MEM, %g4
293 stx %g4, [%g1 + 32] ! byte 32 - 39
295 ldxa [%g3 + %g7]ASI_MEM, %g4
296 stx %g4, [%g1 + 40] ! byte 40 - 47
298 ldxa [%g3 + %g7]ASI_MEM, %g4
299 stx %g4, [%g1 + 48] ! byte 48 - 55
301 ldxa [%g3 + %g7]ASI_MEM, %g4
302 stx %g4, [%g1 + 56] ! byte 56 - 63
303 ldx [%g2 + MCPU_DEV_Q_SIZE], %g4 ! queue size
305 1: sub %g4, 1, %g4 ! %g4 = queue size mask
307 and %g6, %g4, %g6 ! and mask for wrap around
313 TRACE_PTR(%g4, %g6)
315 stxa %g6, [%g4 + TRAP_ENT_TICK]%asi
316 TRACE_SAVE_TL_GL_REGS(%g4, %g6)
318 stha %g6, [%g4 + TRAP_ENT_TT]%asi
320 stna %g6, [%g4 + TRAP_ENT_TPC]%asi
322 stxa %g6, [%g4 + TRAP_ENT_TSTATE]%asi
325 stna %g6, [%g4 + TRAP_ENT_SP]%asi ! Device Queue Base PA
326 stna %g5, [%g4 + TRAP_ENT_TR]%asi ! Inum
329 stna %g6, [%g4 + TRAP_ENT_F1]%asi
331 stna %g6, [%g4 + TRAP_ENT_F2]%asi ! Q Size
332 stna %g7, [%g4 + TRAP_ENT_F3]%asi ! tail offset
333 stna %g0, [%g4 + TRAP_ENT_F4]%asi
334 TRACE_NEXT(%g4, %g6, %g3)
379 mov CPU_RQ_HD, %g4
380 ldxa [%g4]ASI_QUEUE, %g2 ! %g2 = Q head offset
381 mov CPU_RQ_TL, %g4
382 ldxa [%g4]ASI_QUEUE, %g3 ! %g3 = Q tail offset
389 CPU_ADDR(%g1, %g4) ! %g1 = cpu struct addr
391 2: set CPU_RQ_BASE_OFF, %g4
392 ldx [%g1 + %g4], %g4 ! %g4 = queue base PA
393 add %g6, %g4, %g4 ! %g4 = PA of ER in Q
395 add %g4, %g7, %g7 ! %g7=PA of ER in kernel buf
404 ldxa [%g4 + %g5]ASI_MEM, %g1
407 ldxa [%g4 + %g5]ASI_MEM, %g1
410 ldxa [%g4 + %g5]ASI_MEM, %g1
413 ldxa [%g4 + %g5]ASI_MEM, %g1
416 ldxa [%g4 + %g5]ASI_MEM, %g1
419 ldxa [%g4 + %g5]ASI_MEM, %g1
422 ldxa [%g4 + %g5]ASI_MEM, %g1
425 ldxa [%g4 + %g5]ASI_MEM, %g1
442 mov CPU_RQ_HD, %g4
443 stxa %g6, [%g4]ASI_QUEUE ! update head offset
452 rdpr %pil, %g4
453 cmp %g4, PIL_14
455 movl %icc, PIL_14, %g4
464 1: mov CPU_RQ_HD, %g4
465 stxa %g3, [%g4]ASI_QUEUE ! set head equal to tail
476 rdpr %pil, %g4
477 cmp %g4, PIL_14
479 movl %icc, PIL_14, %g4
504 mov CPU_NRQ_HD, %g4
505 ldxa [%g4]ASI_QUEUE, %g2 ! %g2 = Q head offset
506 mov CPU_NRQ_TL, %g4
507 ldxa [%g4]ASI_QUEUE, %g3 ! %g3 = Q tail offset
515 mov CPU_NRQ_HD, %g4
516 ldxa [%g4]ASI_QUEUE, %g2 ! %g2 = Q head offset
517 mov CPU_NRQ_TL, %g4
518 ldxa [%g4]ASI_QUEUE, %g3 ! %g3 = Q tail offset
521 CPU_PADDR(%g1, %g4) ! %g1 = cpu struct paddr
523 2: set CPU_NRQ_BASE_OFF, %g4
524 ldxa [%g1 + %g4]ASI_MEM, %g4 ! %g4 = queue base PA
525 add %g6, %g4, %g4 ! %g4 = PA of ER in Q
527 add %g4, %g7, %g7 ! %g7 = PA of ER in kernel buf
536 ldxa [%g4 + %g5]ASI_MEM, %g1
539 ldxa [%g4 + %g5]ASI_MEM, %g1
542 ldxa [%g4 + %g5]ASI_MEM, %g1
545 ldxa [%g4 + %g5]ASI_MEM, %g1
548 ldxa [%g4 + %g5]ASI_MEM, %g1
551 ldxa [%g4 + %g5]ASI_MEM, %g1
554 ldxa [%g4 + %g5]ASI_MEM, %g1
557 ldxa [%g4 + %g5]ASI_MEM, %g1
574 mov CPU_NRQ_HD, %g4
575 stxa %g6, [%g4]ASI_QUEUE ! update head offset
612 rdpr %tpc, %g4
615 cmp %g4, %g5
619 cmp %g4, %g5
624 rdpr %tt, %g4 ! %g4 = tt[1]
626 and %g4, WTRAP_TTMASK, %g4
627 cmp %g4, WTRAP_TYPE
638 mov 1, %g4
639 sllx %g4, ERRH_U_SPILL_FILL_SHIFT, %g4
640 or %g2, %g4, %g2 ! turn on flag in %g2
645 rdpr %pil, %g4
646 cmp %g4, PIL_14
648 movl %icc, PIL_14, %g4
657 rdpr %pil, %g4
658 cmp %g4, PIL_14
660 movl %icc, PIL_14, %g4