Lines Matching refs:g2
68 ! %g2 arg 2
81 CPU_ADDR(%g1,%g2)
82 add %g1, CPU_MCPU, %g2
83 ldx [%g2 + MCPU_CPU_Q_BASE], %g3 ! %g3 = queue base PA
84 ldx [%g2 + MCPU_CPU_Q_SIZE], %g4 ! queue size
96 ! %g2 arg 2
102 ldxa [%g3 + %g6]ASI_MEM, %g2 ! read data word 2
123 stna %g2, [%g4 + TRAP_ENT_F3]%asi ! arg2
222 ! %g2 arg 2
235 CPU_ADDR(%g1,%g2)
236 add %g1, CPU_MCPU, %g2
237 ldx [%g2 + MCPU_DEV_Q_BASE], %g3 ! %g3 = queue base PA
252 ldx [%g2 + MCPU_DEV_Q_SIZE], %g4 ! queue size - delay slot
270 ldx [%g2 + MCPU_DEV_Q_SIZE], %g4 ! queue size - delay slot
274 ldx [%g2 + MCPU_DEV_Q_SIZE], %g4 ! queue size - delay slot
303 ldx [%g2 + MCPU_DEV_Q_SIZE], %g4 ! queue size
324 ldx [%g2 + MCPU_DEV_Q_BASE], %g6
330 ldx [%g2 + MCPU_DEV_Q_SIZE], %g6
380 ldxa [%g4]ASI_QUEUE, %g2 ! %g2 = Q head offset
383 mov %g2, %g6 ! save head in %g2
447 * Call sys_trap at PIL 14 unless we're already at PIL 15. %g2.l is
469 * Set %g2 to %g6, which is current head offset. %g2
474 mov %g6, %g2
505 ldxa [%g4]ASI_QUEUE, %g2 ! %g2 = Q head offset
509 cmp %g2, %g3
516 ldxa [%g4]ASI_QUEUE, %g2 ! %g2 = Q head offset
519 mov %g2, %g6 ! save head in %g2
579 * Call sys_trap. %g2 is TL(arg2), %g3 is head and tail
590 or %g3, %g2, %g3 ! %g3.l = head offset
591 rdpr %tl, %g2 ! %g2 = current tl
608 cmp %g2, 2
636 * Turn on the user spill/fill flag in %g2
640 or %g2, %g4, %g2 ! turn on flag in %g2
642 3: sub %g2, 1, %g2 ! %g2.l = previous tl