Lines Matching refs:l0
514 ldsb [THREAD_REG + T_PREEMPT], %l0
515 deccc %l0
517 stb %l0, [THREAD_REG + T_PREEMPT]
520 ldn [THREAD_REG + T_CPU], %l0
521 ldub [%l0 + CPU_KPRUNRUN], %l0
522 brnz,a,pt %l0, 1f ! Need to call kpreempt?
2035 ldsb [THREAD_REG + T_PREEMPT], %l0
2036 deccc %l0
2038 stb %l0, [THREAD_REG + T_PREEMPT]
2041 ldn [THREAD_REG + T_CPU], %l0
2042 ldub [%l0 + CPU_KPRUNRUN], %l0
2043 brnz,a,pt %l0, 1f ! Need to call kpreempt?
2199 andn %i1, 0x3f, %l0 ! %l0 has block aligned source
2200 prefetch [%l0+0x0], #one_read
2204 prefetch [%l0+0x40], #one_read
2221 add %l0, 0x40, %l0
2235 andn %i1, 0x3f, %l0 ! %l0 has block aligned source
2236 prefetch [%l0+0x0], #one_read
2243 prefetch [%l0+0x40], #one_read
2264 add %l0, 0x40, %l0
2280 andn %i1, 0x3f, %l0 ! %l0 has block aligned source
2281 prefetch [%l0+0x0], #one_read
2289 prefetch [%l0+0x40], #one_read
2310 add %l0, 0x40, %l0
2325 ldda [%i1+0x0]%asi, %l0
2329 stxa %l0, [%i0+0x0]%asi
2460 ! l0 size in bits of upper part of source word (US)
2472 clr %l0
2481 add %l0, 8, %l0 ! increment size of upper source (US)
2485 sub %l5, %l0, %l1 ! generate shift left count (LS)
2489 srl %i3, %l0, %i5 ! upper src bits into lower dst bits
2502 cmp %l2, %l0 ! cmp # reqd to fill dst w old src left
2509 sub %l0, %l2, %l0 ! regenerate shift count
2510 sub %l5, %l0, %l1 ! generate new shift left count (LS)
2513 srl %i3, %l0, %i4
2523 sll %i3, %l0, %i3 ! save remaining byte(s)
2524 srl %i3, %l0, %i3
2525 sub %l2, %l0, %l1 ! regenerate shift count
2526 sub %l5, %l1, %l0 ! generate new shift left count
2536 mov 24, %l0 ! initial shift alignment count
2538 srl %i4, %l0, %i3 ! prepare to write a single byte
2544 sub %l0, 8, %l0 ! delay slot, decrement shift count
2546 sub %l5, %l0, %l1 ! generate shift left count
2554 srl %i3, %l0, %i4 ! upper src bits into lower dst bits
2567 sub %l0, 8, %l0 ! decrement shift
2568 srl %i3, %l0, %i4 ! upper src byte into lower dst byte
2573 tst %l0 ! any more previously read bytes
2586 add %l0, 8, %l0 ! increment shift count (US)
2779 ldda [%i0+0x0]%asi, %l0
2783 stxa %l0, [%i1+0x0]%asi
2791 ldda [%i0+0x40]%asi, %l0
2795 stxa %l0, [%i1+0x40]%asi
4823 andn %i1, 0x3f, %l0 ! %l0 has block aligned source
4824 prefetch [%l0+0x0], #one_read
4829 prefetch [%l0+0x40], #one_read
4852 add %l0, 0x40, %l0
4866 andn %i1, 0x3f, %l0 ! %l0 has block aligned source
4867 prefetch [%l0+0x0], #one_read
4876 prefetch [%l0+0x40], #one_read
4905 add %l0, 0x40, %l0
4920 andn %i1, 0x3f, %l0 ! %l0 has block aligned source
4921 prefetch [%l0+0x0], #one_read
4931 prefetch [%l0+0x40], #one_read
4961 add %l0, 0x40, %l0
4976 ldda [%i1]ASI_BLK_INIT_ST_QUAD_LDD_P, %l0
4983 stxa %l0, [%i0+0x0]%asi
7001 andn %i1, 0x3f, %l0 ! %l0 has block aligned source
7002 prefetcha [%l0]ASI_USER, #one_read
7004 add %l0, 0x40, %l0
7009 prefetcha [%l0]ASI_USER, #one_read
7032 add %l0, 0x40, %l0
7046 andn %i1, 0x3f, %l0 ! %l0 has block aligned source
7047 prefetcha [%l0]ASI_USER, #one_read
7051 add %l0, 0x40, %l0
7059 prefetcha [%l0]ASI_USER, #one_read
7088 add %l0, 0x40, %l0
7103 andn %i1, 0x3f, %l0 ! %l0 has block aligned source
7104 prefetcha [%l0]ASI_USER, #one_read
7108 add %l0, 0x40, %l0
7115 prefetcha [%l0]ASI_USER, #one_read
7145 add %l0, 0x40, %l0
7161 ldda [%i1]ASI_BLK_INIT_QUAD_LDD_AIUS, %l0
7168 stxa %l0, [%i0+0x0]%asi