Cross Reference: /illumos-gate/usr/src/uts/sun4u/vm/mach_sfmmu

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101  * Invalidate either the context of a specific victim or any process
106  * Note %g1 is the only input argument used by this xcall handler.
193 	! If this is Cheetah or derivative and the specified TTE is locked
194 	! and hence to be loaded into the T16, fully-associative TLB, we
198 	! this erratum, we scan the T16 top down for an unlocked TTE and
199 	! explicitly load the specified TTE into that index.
209 	  or	%g0, (15 << 3), %g3		! Start searching from the
217 	! of the lock bit).
257 	 * Load an entry into the DTLB.
260 	 * are some TLB slots that are reserved for the kernel but not
315 	! of the lock bit).
326 	! for the DTLB.  Erratum 34 states that under certain conditions, 
372 	 * Set the secondary context register for this process.
408 	 * if the routine was entered with intr enabled, then enable intr now.
420 	 * set ktsb_phys to 1 if the processor supports ASI_QUAD_LDD_PHYS.
421 	 * returns the detection value in %o0.
446 	 * for the active process.  This function should
464          * We need to set up the TSB base register, tsbmiss
465          * area, and load locked TTE(s) for the TSB.
473          * TSB is in the MMU I/D TSB Base registers.  The 2nd, 3rd and 
538          * encode data for both the first and second TSB in our single
541          * We also need to load a locked TTE into the TLB for the second TSB
565          * Load the TTE for the first TSB at the appropriate location in
566          * the TLB
578         stx     %o1, [%o2 + TSBMISS_ISMBLKPA]   ! sfmmu_tsb_miss into the
616  * Invalidate all of the entries within the tsb, by setting the inv bit
617  * in the tte_tag field of each tsbe.
619  * We take advantage of the fact TSBs are page aligned and a multiple of
622  * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice
623  * (in short, we set all bits in the upper word of the tag, and we give the
645 	! See if fpu was in use.  If it was, we need to save off the
646 	! floating point registers to the stack.
719  * reads.  However, this has the negative side effect of polluting
720  * the ecache.
729 /* Prefetch the tsbe that we are about to write */